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#1
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Activate Cache in Processors *confussed*
I was just wondering:
If the cache (L1&L2) of a processor are completely invisible for the programmer, being totally controled by hardware, why does Windows (not sure about linux or other O.S) give the option to activate these and even more, why do you get a better performance. Can the Cache be activated de activated? Is it just a tweak? TIA |
#2
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Can the Cache be activated de activated? Is it just a tweak?
Atleast from many BIOS'es it can be. There are instructions in x86 (486 isa),sse,sse2,sse3 to affect cache in various ways, you can find more information from Intel's references for various of their products at developer.intel.com, they have online reference manuals for their x86 implementations, etc. you can also check www.sandpile.org (sp?) and other sites. There are instructions to invalidate cache, read ahead, etc.etc. you must check feature flags of your processor what instructions are supported and then look up from the references what the instructions are supposed to do. This isn't a particularly small topic to cover in a single Usenet post. |
#3
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By default, CPU cache is enabled and Windows doesn't have an option to
disable it altogether. It has an useless option to reduce its size for Pentium-II. BIOS may allow you to disable cache for troubleshooting purposes. "Bulblight" wrote in message om... I was just wondering: If the cache (L1&L2) of a processor are completely invisible for the programmer, being totally controled by hardware, why does Windows (not sure about linux or other O.S) give the option to activate these and even more, why do you get a better performance. Can the Cache be activated de activated? Is it just a tweak? TIA |
#4
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"Alexander Grigoriev" wrote in message hlink.net...
By default, CPU cache is enabled and Windows doesn't have an option to disable it altogether. It has an useless option to reduce its size for Pentium-II. BIOS may allow you to disable cache for troubleshooting purposes. So then, Windows can actually change the set of instructions it requieres to do a certain job depending whether you have the caché activated of not? Can you give an example of a x86 instruction that extensively and explicitly uses cache? Thanks in advance! Cheers |
#5
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#6
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Can you give an example of a x86 instruction that extensively and
explicitly uses cache? 486: wbinvd SSE: maskmovq movntq movntps prefetch(h) sfence SSE2: clflush lfence mfence pause maskmovdqu movntpd movntdq movnti ... those are some, I posted my cheating list to my website: www.liimatta.org/misc/wogsimd.txt Visit developer.intel.com for references what each instruction does. I only use that list as "cheat", when I don't remember the precise instruction mnemonics. SSE3 adds more instructions but I haven't obviously updated my cheat list yet to cover those (I will when I get the CPU, speaking of which, that's why I chose P4 originally over Athlon, to be able to program for SSE2, not because AthlonXP (?) at the time was few % faster than a P4 Anyways, I gave you URLs to in other post already, what was wrong with them? Didn't find anything? |
#7
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SSE2, not because AthlonXP (?) at the time was few % faster than a P4
A quick mental lookup gives impression that it was Athlon TB which was the alternative back then, I could remember still wrong so correct me if feel inclined. I've got a bad memory and even worse when placing two different things simultaneously on a timeline. Especially since I never been a into Athlons to begin with. Cheap, sure, so what. |
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