effect of DIMM voltage on temperatures?

Suppose one raises the memory voltage for whatever reason.
Now I presume that would raise the temperature of the DIMMS (unless the CPU
was idle begging for work). Would it also raise the CPU temperature,
with internal memory controllers, as used since K8 and Nehalem?

wrote:
Suppose one raises the memory voltage for whatever reason.
Now I presume that would raise the temperature of the DIMMS (unless the CPU
was idle begging for work). Would it also raise the CPU temperature,
with internal memory controllers, as used since K8 and Nehalem?

This is a general power formula, suitable for I/O power
and for CMOS core logic. F is the toggle frequency (1-0-1-0
pattern). C is the node capacitance. V1 is the signal amplitude.
V2 is the power rail voltage. For CMOS core logic, V1 and V2
are roughly the same.

F*C*V1*V2

So for the CMOS core, this is an approximation. V1 = V2 = V

F*C*V^2

When doing estimates, I used to run digital circuits through
an analog simulator, to get some realistic numbers. That's
to prevent accounting errors :-)

*******

Rather than give a lot of hand waving, which may or
may not be true, I'll just say the IMC should experience
insignificant heating on I/O power. The IMC core logic
should continue to run at approximately 1 volt. The
control/address pads, the power on those scales with V^2 ,
but the duty cycle isn't all that high, and the power
of those I/O pads compared to the 95W CPU core power,
is minimal.

*******

I don't really expect to find enough info in the datasheets,
to refine this answer for you. And the last "reference schematic"
I was able to get, was for DDR400. I have nothing to look
at for DDR2, DDR3, DDR4. When I was working, I'd just wave
my business card, and I could get collateral materials
(sent under NDA).

Things that are much more significant, would be FIVR on Haswell,
which is a power regulator inside the CPU chip. That raises
the power by, like, 20%. And later chips don't
do that any more. It's as much of a puzzle as to why Intel
used FIVR in the first place, as it is for FIVR to disappear
again. Usually when you put that much effort and "proving"
into a thing, you keep the technology. So I don't know
what caused FIVR to be rejected for the next spin. It's
certainly inconvenient to have that stuff in the same
package with the CPU die.

Your CPU could become unstable, just from corrupt data
being sampled from the high-clocked DRAM. If you wanted
to study this in a slightly more controlled way, you
might want a CPU with ECC on the memory bus. To make it
easier to log ECC events as an indicator the DRAM interface
isn't feeling well. Unfortunately, on Intel, it's really hard
to get hardware like that (have to use Xeon). AMD is much
more generous with ECC.

Paul

On 15/03/2017 9:38 PM, wrote:
Suppose one raises the memory voltage for whatever reason.
Now I presume that would raise the temperature of the DIMMS (unless the CPU
was idle begging for work). Would it also raise the CPU temperature,
with internal memory controllers, as used since K8 and Nehalem?


Heat is always an issue, especially when you overclock them using
higher than default voltage. That's why some RAM modules have heatsinks.

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