Gaming AMD vs Intel

On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald
wrote:

....snip...
If we allow a bit of slack and call the on-die L2 cache connection a BSB,
we can call the K7s', P4s', P-Ms' connection to the chipset a FSB - after
all it carries the same traffic as a FSB. AMD has used this terminology
for its K7 architecture though some have argued with that. With the K8 the
HT link to to the I/O sub-system, however, there is no CPU- memory
traffic, which is the principal function of a FSB and is the derivation of
the name; the up/down HT link doesn't even serve the same functions as a
FSB.

....snip...

"no CPU- memory traffic"
Correct for uniprocessor system. As soon as we get to dual (trust me
on this - I'm typing this on 2x Opteron 242 on MSI master2-far board)
HT starts carrying CPU- memory traffic. It is especially true in
case of more than half dual Opty board out there (including mine)
where all RAM is hanging off one CPU, and the other accesses it
through HT.

NNN

On Sun, 11 Sep 2005 05:25:33 GMT, Wes Newell
wrote:

"In computer architecture, a bus is a subsystem that transfers data or
power between computer components inside a computer or between
computers. Unlike a point-to-point connection, a bus can logically
connect several peripherals over the same set of wires."

But if you use this definition, there was never a FSB, or BSB bus
as these were both point to point connections. Was not the FSB of the
original Pentium Pro point to point (cpu to chipset)?

No it most definitely was not. You could hang up to 4 PPro processors
off the same bus.

And this defintition
also disagrees with lots of other definitions of bus, and lastly, if my
system has only one memory slot, does that mean my system doesn't have a
memory bus?

If you're using SDRAM or DDR SDRAM then the bus connects to each
individual chip on the module. Unless you've only got a single memory
chip on your single DIMM then this is definitely not a direct
point-to-point connection.

Besides, it's more a question of what the bus is capable of, not so
much what it is actually being used for. Just because the P4
processor itself is only capable of working in a single-processor
setup doesn't change the fact that the AGTL+ bus that it uses can be
used for up to 4 processors on the same bus (as seen in some Xeon
systems).

-------------
Tony Hill
hilla underscore 20 at yahoo dot ca

"Tony Hill" wrote in message
...
On Sun, 11 Sep 2005 05:25:33 GMT, Wes Newell
wrote:

"In computer architecture, a bus is a subsystem that transfers data or
power between computer components inside a computer or between
computers. Unlike a point-to-point connection, a bus can logically
connect several peripherals over the same set of wires."

But if you use this definition, there was never a FSB, or BSB bus
as these were both point to point connections. Was not the FSB of the
original Pentium Pro point to point (cpu to chipset)?

No it most definitely was not. You could hang up to 4 PPro processors
off the same bus.

And this defintition
also disagrees with lots of other definitions of bus, and lastly, if my
system has only one memory slot, does that mean my system doesn't have a
memory bus?

If you're using SDRAM or DDR SDRAM then the bus connects to each
individual chip on the module. Unless you've only got a single memory
chip on your single DIMM then this is definitely not a direct
point-to-point connection.

Besides, it's more a question of what the bus is capable of, not so
much what it is actually being used for. Just because the P4
processor itself is only capable of working in a single-processor
setup doesn't change the fact that the AGTL+ bus that it uses can be
used for up to 4 processors on the same bus (as seen in some Xeon
systems).


You guys must be a barrel of laughs down the pub.... ;-)

Could ya knock of the non-technical game group from future posts pls?

On Sun, 11 Sep 2005 13:52:36 -0500, Big_Pig wrote:

Since there is no FSB to use as a reference for the CPU-core's
clockspeed (as well as some of the other clocks), we need something else
to provide the required reference clock signal.

The solution to this problem is a 200MHz base-clock provided to the
processor by the on-board clock-generator on all 8th-Generation
platforms.

And that's exactly how previous generations platforms did it too.:-)

This Article will explain how clocks are generated on an AMD
8th-Generation platform.
http://forums.amd.com/index.php?showtopic=55881

This is a great article, but there's really no difference in the system
clock source of the K7 and K8. They both use the clkin signals. Previously
this clock was called FSB frequency or FSB clock or whatever a board
manufacurer wanted to use to set the clock generator. I think most used
FSB Frequency, but I haven't looked at all the boards bioses. So now comes
the K8 and in their wisdom (or lack of it IMO), thee decide the new bus
type of HT link shouldn't use FSB as the name like the previous K7 EV6
type bus. And that would have been fine if they would come up with another
name to set this clock. I haven't looked at many K8 boards, but it's
designated as System Bus in my bios. The big problem with that name is
that a system bus can any in the system, and isn't specific enough. Same
goes for HT link, which is really a name for a technology like EV6 is, and
is used in many applications than just the K8 CPU's. Not to mention there
can be multiple HT links in a system, so how do you know which one they're
talking about unless it spelled out. Looking back, it would have been
much better to use something like System Clock Gen or CPU Clock Gen for
this setting rather than FSB, but since we were shouldered with FSB, it
finally became known as the connection between the CPU and chipset, which
in fact it is, and that this was the setting to chnage to set the internal
cpu clock... Now that there's no FSB designated for the K8, there's also
no desgination one would easily recognize. So did AMD do away with the
FSB, or just the name because they wanted more exposure for HT or some
other reason. I contend, it was just the name they wanted to change since
the actual traces on the MB still go from the CPU to the chipset just like
previous FSB's with the exception of the memory bus. Had they keep the FSB
name, or even called it the HT FSB, there wouldn't have been the confusion
there is now. Fankly I don't care much. But since many peole don't like
the term FSB used with the K8, I'm going to start telling people to raise
the clkin frequency to the cpu to set the cpu speed and let them worry
about what there board maker called it in the bios. Now since the FSB
term was used to set clkin on previous cpu's, why is it now all of a
sudden taboo?

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

Your entire premise is wrong.

Hypertransport is a High speed, packet based control and communication
protocol. It supports the Direct Connect Architecture of the AMD Athlon64
and Turion64 processors. The processor does not use the Northbridge to
communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there. The
traditional Northbridge legacy set is handled by the chip, as is the
Southbridge, but for the Proc, RAM and video there is no FSB, just the
speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition, the
communication is duplex under Hypertransport, versus simplex under NB-FSB.

Bobby

"Wes Newell" wrote in message
newsan.2005.09.11.23.37.45.362968@TAKEOUTverizon .net...
On Sun, 11 Sep 2005 13:52:36 -0500, Big_Pig wrote:

Since there is no FSB to use as a reference for the CPU-core's
clockspeed (as well as some of the other clocks), we need something else
to provide the required reference clock signal.

The solution to this problem is a 200MHz base-clock provided to the
processor by the on-board clock-generator on all 8th-Generation
platforms.

And that's exactly how previous generations platforms did it too.:-)

This Article will explain how clocks are generated on an AMD
8th-Generation platform.
http://forums.amd.com/index.php?showtopic=55881

This is a great article, but there's really no difference in the system
clock source of the K7 and K8. They both use the clkin signals. Previously
this clock was called FSB frequency or FSB clock or whatever a board
manufacurer wanted to use to set the clock generator. I think most used
FSB Frequency, but I haven't looked at all the boards bioses. So now comes
the K8 and in their wisdom (or lack of it IMO), thee decide the new bus
type of HT link shouldn't use FSB as the name like the previous K7 EV6
type bus. And that would have been fine if they would come up with another
name to set this clock. I haven't looked at many K8 boards, but it's
designated as System Bus in my bios. The big problem with that name is
that a system bus can any in the system, and isn't specific enough. Same
goes for HT link, which is really a name for a technology like EV6 is, and
is used in many applications than just the K8 CPU's. Not to mention there
can be multiple HT links in a system, so how do you know which one they're
talking about unless it spelled out. Looking back, it would have been
much better to use something like System Clock Gen or CPU Clock Gen for
this setting rather than FSB, but since we were shouldered with FSB, it
finally became known as the connection between the CPU and chipset, which
in fact it is, and that this was the setting to chnage to set the internal
cpu clock... Now that there's no FSB designated for the K8, there's also
no desgination one would easily recognize. So did AMD do away with the
FSB, or just the name because they wanted more exposure for HT or some
other reason. I contend, it was just the name they wanted to change since
the actual traces on the MB still go from the CPU to the chipset just like
previous FSB's with the exception of the memory bus. Had they keep the FSB
name, or even called it the HT FSB, there wouldn't have been the confusion
there is now. Fankly I don't care much. But since many peole don't like
the term FSB used with the K8, I'm going to start telling people to raise
the clkin frequency to the cpu to set the cpu speed and let them worry
about what there board maker called it in the bios. Now since the FSB
term was used to set clkin on previous cpu's, why is it now all of a
sudden taboo?

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

On Mon, 12 Sep 2005 01:21:57 +0000, NoNoBadDog! wrote:

Your entire premise is wrong.

Hypertransport is a High speed, packet based control and communication
protocol. It supports the Direct Connect Architecture of the AMD Athlon64
and Turion64 processors. The processor does not use the Northbridge to
communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there. The
traditional Northbridge legacy set is handled by the chip, as is the
Southbridge, but for the Proc, RAM and video there is no FSB, just the
speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition, the
communication is duplex under Hypertransport, versus simplex under NB-FSB.

You're just a little more than confused. The CPU doesn't support AGP, PCI,
PCI-E or much of anything else except the ram directly. The rest still are
still functions of the chipset. The only thing that the CPU now supports
directly is the memory. All other system devices/buses are handled the
same way as the K7 was, over the FSB, or if you prefer, the HT Link
between the cpu and chipset.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

On Sun, 11 Sep 2005 14:59:32 GMT, "
wrote:

On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald
wrote:

...snip...
If we allow a bit of slack and call the on-die L2 cache connection a BSB,
we can call the K7s', P4s', P-Ms' connection to the chipset a FSB - after
all it carries the same traffic as a FSB. AMD has used this terminology
for its K7 architecture though some have argued with that. With the K8 the
HT link to to the I/O sub-system, however, there is no CPU- memory
traffic, which is the principal function of a FSB and is the derivation of
the name; the up/down HT link doesn't even serve the same functions as a
FSB.

...snip...

"no CPU- memory traffic"
Correct for uniprocessor system. As soon as we get to dual (trust me
on this - I'm typing this on 2x Opteron 242 on MSI master2-far board)
HT starts carrying CPU- memory traffic. It is especially true in
case of more than half dual Opty board out there (including mine)
where all RAM is hanging off one CPU, and the other accesses it
through HT.

Of course but that's really CPU-CPU traffic... which is why I made a
point of clearly specifying the "HT link to the I/O sub-system". Lifting
quoted text out of context only confuses the issue.

--
Rgds, George Macdonald

On Sun, 11 Sep 2005 13:52:36 -0500, Big_Pig wrote:

Since there is no FSB to use as a reference for the CPU-core's
clockspeed (as well as some of the other clocks), we need something else
to provide the required reference clock signal.

The solution to this problem is a 200MHz base-clock provided to the
processor by the on-board clock-generator on all 8th-Generation
platforms.

This Article will explain how clocks are generated on an AMD
8th-Generation platform.
http://forums.amd.com/index.php?showtopic=55881

This one doesn't have any mistakes:-) -
http://www.amd.com/us-en/assets/cont.../24707_PUB.PDF

--
Rgds, George Macdonald

"Wes Newell" wrote in message
newsan.2005.09.12.06.11.55.449547@TAKEOUTverizon .net...
On Mon, 12 Sep 2005 01:21:57 +0000, NoNoBadDog! wrote:

Your entire premise is wrong.

Hypertransport is a High speed, packet based control and communication
protocol. It supports the Direct Connect Architecture of the AMD
Athlon64
and Turion64 processors. The processor does not use the Northbridge to
communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there.
The
traditional Northbridge legacy set is handled by the chip, as is the
Southbridge, but for the Proc, RAM and video there is no FSB, just the
speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition,
the
communication is duplex under Hypertransport, versus simplex under
NB-FSB.

You're just a little more than confused. The CPU doesn't support AGP, PCI,
PCI-E or much of anything else except the ram directly. The rest still are
still functions of the chipset. The only thing that the CPU now supports
directly is the memory. All other system devices/buses are handled the
same way as the K7 was, over the FSB, or if you prefer, the HT Link
between the cpu and chipset.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

Re-read what I wrote...I did not say that it did, but that the
hypertransport bus allows greater bandwidth and duplex operations. The
memory controller accesses the cache and RAM data.
The NB is legacy, while the SB still functions in a traditional manner.

Bobby

On Mon, 12 Sep 2005 06:07:42 GMT, Wes Newell
wrote:

On Mon, 12 Sep 2005 01:21:57 +0000, NoNoBadDog! wrote:

Your entire premise is wrong.

Hypertransport is a High speed, packet based control and communication
protocol. It supports the Direct Connect Architecture of the AMD Athlon64
and Turion64 processors. The processor does not use the Northbridge to
communicate to Memory/AGP/PCI/PCI-E, so there is *no* FSB speed there. The
traditional Northbridge legacy set is handled by the chip, as is the
Southbridge, but for the Proc, RAM and video there is no FSB, just the
speed/bandwidth of the H/T bus (800, 1000, 1600 or 2000). In addition, the
communication is duplex under Hypertransport, versus simplex under NB-FSB.

You're just a little more than confused. The CPU doesn't support AGP, PCI,
PCI-E or much of anything else except the ram directly. The rest still are
still functions of the chipset. The only thing that the CPU now supports
directly is the memory. All other system devices/buses are handled the
same way as the K7 was, over the FSB, or if you prefer, the HT Link
between the cpu and chipset.

You have just proved your complete misunderstanding of what is on the K8
die and what the HT I/O-link is used for. All CPU memory accesses mapped
to I/O devices, such as AGP/PCI-e, or any PCI device must be trapped in the
CPU's "north bridge" sub-set and diverted to the HT I/O link; obviously the
corresponding MTRRs and associated logic *must* be on the CPU die. Same
for CPU cache snooping - previously a north bridge/FSB function and now
incorporated into the CPU.

Apart from CPU I/O reads/writes and interrupts, a minor part of FSB traffic
"volume", the HT I/O link has nothing in common with a FSB. The major
volume of traffic on the K8 HT I/O-link, viz. DMA transfers, is handled and
routed internally in the north bridge (MC Hub) of a FSB type system.

--
Rgds, George Macdonald