Gaming AMD vs Intel

Wes Newell wrote:
: On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:
:
snip

::
:: The last paragraph you quote, shown above, is Clintonian at best,
:: with respect to comparing the physical aspects of HT and PCI-E.
:
: You snipped the portion I had highlighted. I didn't even read this
: part. Nor do I have any comments on it. If you have a problem with
: it. i suggest you contact the people that wrote it. If Clintonian
: refers to refers to our lying crooked x pres, those are are
: fighting words. I never voted for the lowlife.

Oh how interesting. So you voted for the current crooked, lying
president? Oops, forgot to throw in "incompetent" as he gives a whole new
meaning to the word. LOL!

j.

"keith" wrote in message
news
On Fri, 09 Sep 2005 22:59:53 -0400, Tony Hill wrote:

On Fri, 09 Sep 2005 11:29:38 -0400, keith wrote:

On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:

On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
wrote:

Not true at all. The original AMD Athlon had both a front-side bus,
connecting the CPU to the chipset, I/O and memory, and a backside
bus
that connected the CPU to the cache chips on the Slot-A cartridge.
This was actually the last x86 CPU that I'm aware of which did have
a
frontside bus (Intel had already gone to integrated cache by this
time).

Just because the cache is integrated doesn't mean the cache isn't on
the
"back side" of the processor. The "back-side" concept was really a
separation of the cache from the memory busses.

Ok, I'll grant that point. I would still say that it's not really an
accurate way of describing things when your 'bus' is connecting one
half of a die to the other half of the die, but I suppose it is still
a 'bus' of sorts, and certainly would be on the "backside" (relative
to memory).

Why? There are *loads* of busses on processor chips, though most are
driven from a single end (bi-di gets messy). ...right down to the
power busses, though sometimes they're grids. ;-)

--
Keith

And people talk about the power bus even when it is a grid. Just like
they talk about the clock tree when it is a grid. And real designers
sometimes talk about the HT bus or the RIO bus, or the GX bus even when
it is a link more than a bus.

del

On Sat, 10 Sep 2005 02:43:11 GMT, Wes Newell
wrote:

On Fri, 09 Sep 2005 18:23:25 -0400, George Macdonald wrote:

On Fri, 09 Sep 2005 04:52:36 GMT, Wes Newell
wrote:
You're out to lunch here for the most part.

If you go look up some tech docs & data sheets you'll find that he's spot
on... as usual. EV6 is not a bus by the usual criteria.

Suggest you read this. One of thousands that claim it's a bus.

http://www.free-definition.com/Front-side-bus.html

But you forgot to read it: under HyperTransport: "Not technically a front
side bus".titter

Wrong. FSB is defined as the bus connection between the CPU and chipset.
AMD calls the bus a FSB and I'm pretty sure Intel did too on the P4.

You'll have to cite a technical reference for AMD calling the HT link to
the I/O chip(s) a FSB - brewing up your own folksy lexicon for computer
sub-system nomenclature will not do it.

I'm not wasting any more time citing crap for you. The proof is down
below, which you tend to ignore.

A FAQ is *not* a tech reference.

If
you break down the term, it's pretty simple. Front side, meaning not the
back side, and bus. A bus is a collection of 1 or more electrical
connections between 2 or more points. The type of bus (standard, EV6, HT
link, or any other type) is of no concern.

If we allow a bit of slack and call the on-die L2 cache connection a
BSB, we can call the K7s', P4s', P-Ms' connection to the chipset a FSB -
after all it carries the same traffic as a FSB. AMD has used this
terminology for its K7 architecture though some have argued with that.
With the K8 the HT link to to the I/O sub-system, however, there is no
CPU- memory traffic, which is the principal function of a FSB and is
the derivation of the name; the up/down HT link doesn't even serve the
same functions as a FSB.

The cpu to system memory function was just one of many functions the FSB
does. it still has cpu to memory functions and feeds data to/from the
memory on the video card, the cache memory on each hard drive, memory on
other cards, etc, etc, etc.

The CPU-main-memory traffic is by far the principle function of FSB...
and *is* what the name FSB is derived from. Those others are all I/O and
even where memory mapped, as for video, further illustrate the fact that
north bridge functionality has been implemented in the CPU die.

What? The northbridge has much more in it than just a memory controller.
And the K8 northbridge doesn't even have a memory controller in it.

coughsplutter You just fell in.

I meant the chipset northbridge.

See below - no such animal!

The K8 architecture does not have a north bridge... and in the case of
nForce3/4 has only the one chip for I/O and AGP/PCI-e Tunnel.

Just out of curiosty, I'd like you to tell me what the name of the bus
is between the CPU and the chipset. And I don't mean what type of bus.
It's already known to be an HT link. So what's the name you want to give
it so that when someone refers to it by that name they will know exactly
which bus you are talking about and where it connects. And it has to be
specific. Sytem bus doesn't cut, there's many system buses. CPU bus
doesn't cut it as there are many cpu busses if you count the internal
busses. I say FSB. I'm waiting for a better one from you.

AMD has used the term "I/O connection" when HT connects the CPU to an
I/O chipset; before Pentium Pro it was called system bus or IIRC main
bus or even main system bus.

So, I'm supposed to tell someone that the CPU clockspeed is determined by
the multiplier times the I/O connection speed. Right.:-) Would you care to
guess how many I/O connections there are in a basic PC system, 100,
1000, more than that?:-)

You can call it the "(system) base clock", which is what it is.

I'll give you two options. Take your pick. (1) The internal bus to the
L2 cache is the back side bus. It just internal now. (2) Why must there
be a BSB at all? FSB is more of a designation for a certain bus rather
than actually describing it's location. It connects between the CPU and
chipset, just as it did on the Athlon (non 64) cpu's. And no one had any
complaints of calling it a FSB then. That's what AMD called it.

Again, the most important task of a FSB has been CPU-memory traffic -
the K8's HT doesn't do that... different topology... it's not an FSB.

Actually you can get a functioning system without external ssytem memory.
I'd sure like to see you use a system without a video output, or a storage
device, or any of the other functions that go over the FSB. They have
them, but they're usually used in standalone places as embedded. So, to
me, the memory is not the most important function, but even if it was,
it's still just ONE of many.

We're talking about (AMD) PC architecture here.

It makes all the sense in the world defined as the connection between
the CPU and chipset. If not, tell me what does. All you people have said
it's not right, yet none of you have come up with a definitive name for
the bus. I wonder if that's why it's stuck around so long, since I've
seen it defined as just that, the bus between the CPU and chipset.

No it makes no sense at all, since by definition, as the cohort of a
BSB, it carries CPU-memory traffic. To belabor the point: the BSB
carried CPU-L2 Cache traffic and on cache misses, the traffic is
"diverted" to FSB.

So, if it's not a FSB because the memory bus is now seperate, then the
memory bus is the FSB. Now I'm wondering what I'm going to call my car
when I take the removable dvd player out of it. Can't call it a car
anymore can I. Lost the cigar lighter, no more car.:-)

You must be Irish...?... or drunk?

If you look at
http://www.amd.com/us-en/assets/cont...ure_FINAL2.pdf
on p8 you'll find "Replacing what has traditionally been the system
'front-side bus' with a HyperTransport technology-based I/O connection
dramatically extends processor to system communication bandwidth from
2.1GB/s up to 6.4GB/s". There are pictures for you of the old FSB
architecture and the new HT-based architecture. Then on p9:
"HyperTransport technology provides a high-speed, chip-to-chip
interconnect..."

Sorry, my K8 system isn't designed the same way as it is in the diagram
you reference, and I doubt yours is either. Look at it closely. look at
the northbridge, and then look at the other side. What's changed other
than the name? One thing, the memory bus moved to the cpu.

And that is a *BIG* change - think about it: the principle function of the
CPU-HT-link is now to carry all DMA traffic between I/O devices and
main-memory, in both directions... not a FSB function at all... bears no
resemblance.

Let's see. I've proven the HT link can be a bus. I've proven the HT link
is a FSB when connected betwen the cpu and chipset. That's it for me. if
you need proof from someone other than the people that develope HT
technology you'll have to get it elsewhere.

All you've proven is that you don't know what an FSB is nor what part it
plays in a PC system.

--
Rgds, George Macdonald

On Sat, 10 Sep 2005 07:37:13 GMT, Wes Newell
wrote:

It calls it a bus (a Front Side bus at that) in the portion you snipped
out and you know it. I don't know why you cut it out. it only makes you
look trollish. Here's some more info for you.

http://www.free-definition.com/Front-side-bus.html

Hmm, from this link, at the bottom of the chart:

"*** - Athlon 64, FX, and Opteron processors have a memory controller
on the CPU die, which replaces the traditional FSB"

http://www.free-definition.com/category/Computer_bus

Try this one:

http://www.free-definition.com/Computer-bus.html

"In computer architecture, a bus is a subsystem that transfers data or
power between computer components inside a computer or between
computers. Unlike a point-to-point connection, a bus can logically
connect several peripherals over the same set of wires."

Hypertransport is a point-to-point connection, as is PCI-Express.
GTL+ and PCI are buses.

-------------
Tony Hill
hilla underscore 20 at yahoo dot ca

On Sat, 10 Sep 2005 08:33:53 GMT, Wes Newell
wrote:

On Fri, 09 Sep 2005 23:18:00 -0400, keith wrote:
There is no such "proof". The definition of a "bus" is much older than
even you. A buss is a multi-drop utility. ...kinda like what you take to
work. A point-to-point facility is never referred to as a "bus".

You wouldn't know the definition if it bit you on the ass. But, just to
show how stupid this response is, the frontside bus was point to point, as
was the back side bus. The same could be said for the memory bus. IOW's
you don't know wtf you are talking about.

Uhh ?!?! The GTL bus used in the PPro was DEFINTIELY a multi-point
bus. You can hang up to 4 CPUs off of that bus. This is still true
(at least in some situations) for the AGTL+ bus that Intel still uses
for their P4 and Xeon CPUs.

Similarly the backside bus in the PPro, PII and early PIII chips could
definitely have more than one memory device hung off the back of it.
If my memory is serving me, some Xeon CPUs had up to 4 cache chips on
a single bus. You can't do that with a point-to-point link!

Keeping up with the memory bus it DEFINITELY is a multidrop bus with
only one popular exception that I'm aware of (RDRAM). How else do you
think you can hang more than one DIMM off a single memory bus?

EV6, on the other hand, was not a bus by the strict multidrop
definition of things in that you could NOT hang more than one
processor off the bus. That's why AthlonMP systems (and DEC/Compaq/HP
Alpha systems before it) had one bus per processor. This is a large
part of the reason why you never saw quad AthlonMP systems, only dual
processor ones. Now, that being said, EV6 resembled a bus in most
other respects, which is why I said that it kind of blurred the lines
between a traditional bus and a strictly point-to-point connection.


Now, just how strictly one follows some of these definitions of what a
"bus" is depends on the reader. I know many people (myself included)
would tend to take shortcuts most of the time. Generally speaking I
would quite freely refer to EV6 as a "bus" rather than going through
the above explanation. I'm sure I've even been known to call
PCI-Express or Hypertransport a "bus" from time to time, though I
still recognize that it's not correct.


9. How does HyperTransport technology compare to other bus technologies?

*this is the relevent part*
HyperTransport was designed to support both CPU-to-CPU communications as
well as CPU-to-I/O transfers, thus, it features very low latency.
Consequently, it has been incorporated into multiple x86 and MIPS
architecture processors as an integrated front-side bus.

That's rather poorly worded on their part and actually contradicts
other parts of the same article where they (correctly) state that
Hypertransport is not a bus at all. As mentioned above though, people
take shortcuts, sometimes even when they know it's not really correct.

-------------
Tony Hill
hilla underscore 20 at yahoo dot ca

On Sat, 10 Sep 2005 17:25:17 +0200, jack wrote:

Wes Newell wrote:
: On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:
:
snip

::
:: The last paragraph you quote, shown above, is Clintonian at best,
:: with respect to comparing the physical aspects of HT and PCI-E.
:
: You snipped the portion I had highlighted. I didn't even read this
: part. Nor do I have any comments on it. If you have a problem with
: it. i suggest you contact the people that wrote it. If Clintonian
: refers to refers to our lying crooked x pres, those are are
: fighting words. I never voted for the lowlife.

Oh how interesting. So you voted for the current crooked, lying
president? Oops, forgot to throw in "incompetent" as he gives a whole new
meaning to the word. LOL!


....and your contribution here is??? Yutz! LOL!

--
Keith

j.

On Sat, 10 Sep 2005 11:29:47 -0500, Del Cecchi wrote:


"keith" wrote in message
news
On Fri, 09 Sep 2005 22:59:53 -0400, Tony Hill wrote:

On Fri, 09 Sep 2005 11:29:38 -0400, keith wrote:

On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:

On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
wrote:

Not true at all. The original AMD Athlon had both a front-side bus,
connecting the CPU to the chipset, I/O and memory, and a backside
bus
that connected the CPU to the cache chips on the Slot-A cartridge.
This was actually the last x86 CPU that I'm aware of which did have
a
frontside bus (Intel had already gone to integrated cache by this
time).

Just because the cache is integrated doesn't mean the cache isn't on
the
"back side" of the processor. The "back-side" concept was really a
separation of the cache from the memory busses.

Ok, I'll grant that point. I would still say that it's not really an
accurate way of describing things when your 'bus' is connecting one
half of a die to the other half of the die, but I suppose it is still
a 'bus' of sorts, and certainly would be on the "backside" (relative
to memory).

Why? There are *loads* of busses on processor chips, though most are
driven from a single end (bi-di gets messy). ...right down to the
power busses, though sometimes they're grids. ;-)

--
Keith

And people talk about the power bus even when it is a grid. Just like
they talk about the clock tree when it is a grid. And real designers
sometimes talk about the HT bus or the RIO bus, or the GX bus even when
it is a link more than a bus.

People call cyan, blue too. Because people get sloppy, doesn't change the
meaning of words. In technical writing, words do have meanings.

--
Keith

del

"keith" wrote in message
news
On Sat, 10 Sep 2005 11:29:47 -0500, Del Cecchi wrote:


"keith" wrote in message
news
On Fri, 09 Sep 2005 22:59:53 -0400, Tony Hill wrote:

On Fri, 09 Sep 2005 11:29:38 -0400, keith wrote:

On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:

On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
wrote:

Not true at all. The original AMD Athlon had both a front-side
bus,
connecting the CPU to the chipset, I/O and memory, and a backside
bus
that connected the CPU to the cache chips on the Slot-A cartridge.
This was actually the last x86 CPU that I'm aware of which did
have
a
frontside bus (Intel had already gone to integrated cache by this
time).

Just because the cache is integrated doesn't mean the cache isn't on
the
"back side" of the processor. The "back-side" concept was really a
separation of the cache from the memory busses.

Ok, I'll grant that point. I would still say that it's not really
an
accurate way of describing things when your 'bus' is connecting one
half of a die to the other half of the die, but I suppose it is
still
a 'bus' of sorts, and certainly would be on the "backside" (relative
to memory).

Why? There are *loads* of busses on processor chips, though most are
driven from a single end (bi-di gets messy). ...right down to the
power busses, though sometimes they're grids. ;-)

--
Keith

And people talk about the power bus even when it is a grid. Just like
they talk about the clock tree when it is a grid. And real designers
sometimes talk about the HT bus or the RIO bus, or the GX bus even
when
it is a link more than a bus.

People call cyan, blue too. Because people get sloppy, doesn't change
the
meaning of words. In technical writing, words do have meanings.

--
Keith
Well, you wanna be picky, cyan is blue. And taupe is tan. And a link is
a bus. Just a special case is all. Just what is the difference? If I
only have two pins on a bus connection, like many PCI-X implementations,
does that make it not a bus?

I was just reporting what folks I hang around with during the week say.
What's the big deal? Saying HT is a link is more specific than saying it
is a bus, but I consider it to also be a bus. It's a floor wax and a
dessert topping.

del

On Sat, 10 Sep 2005 17:25:17 +0200, jack wrote:

Wes Newell wrote:
: On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:
:
snip

::
:: The last paragraph you quote, shown above, is Clintonian at best,
:: with respect to comparing the physical aspects of HT and PCI-E.
:
: You snipped the portion I had highlighted. I didn't even read this
: part. Nor do I have any comments on it. If you have a problem with
: it. i suggest you contact the people that wrote it. If Clintonian
: refers to refers to our lying crooked x pres, those are are
: fighting words. I never voted for the lowlife.

Oh how interesting. So you voted for the current crooked, lying
president? Oops, forgot to throw in "incompetent" as he gives a whole new
meaning to the word. LOL!

I hate to tell you this, but the current president, G. Bush never ran
against Clinton. If you want to comment on something or throw a dig at
someone, it helps if you know wtf you are talking about. That said, I sure
as hell didn't vote for Gore.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

On Sat, 10 Sep 2005 19:21:36 -0400, Tony Hill wrote:

On Sat, 10 Sep 2005 07:37:13 GMT, Wes Newell
wrote:

It calls it a bus (a Front Side bus at that) in the portion you snipped
out and you know it. I don't know why you cut it out. it only makes you
look trollish. Here's some more info for you.

http://www.free-definition.com/Front-side-bus.html

Hmm, from this link, at the bottom of the chart:

"*** - Athlon 64, FX, and Opteron processors have a memory controller
on the CPU die, which replaces the traditional FSB"

Note the wording. It doesn't say it replaces the FSB. It says it replaces
the traditional FSB. The FSB is still there, jst not in a tradidtional
sense, since the memory has it's own path now. I'll tell you what. You can
call it whatever you like, and I'll do the same.

http://www.free-definition.com/category/Computer_bus

Try this one:

http://www.free-definition.com/Computer-bus.html

"In computer architecture, a bus is a subsystem that transfers data or
power between computer components inside a computer or between
computers. Unlike a point-to-point connection, a bus can logically
connect several peripherals over the same set of wires."

But if you use this definition, there was never a FSB, or BSB bus
as these were both point to point connections. Was not the FSB of the
original Pentium Pro point to point (cpu to chipset)? And this defintition
also disagrees with lots of other definitions of bus, and lastly, if my
system has only one memory slot, does that mean my system doesn't have a
memory bus? One sometimes one has to think logical rather than just take
something at face value.

Hypertransport is a point-to-point connection, as is PCI-Express. GTL+
and PCI are buses.

Along with HyperTransport, PCI-Express is also defined as a Computer bus.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm