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Rambus aims for 1 TeraByte per second memory bandwidth by 2010



 
 
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  #11  
Old December 10th 07, 10:37 PM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
John Ahlstrom
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Posts: 3
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

Ken Hagan wrote:
On Fri, 07 Dec 2007 22:51:06 -0000, daytripper
wrote:

So, in short, you don't think the biggest problem confronting
processor design and performance isn't important because "it's hard"...

/daytripper (well, that's one way to go, I guess ;-)


I dunno if its a fair summary of Robert's position, but it is a fair
piece of strategy. It is silly to try to solve an impossible problem.
It is almost as silly to try to solve an almost impossible problem.



How about
It's not important because it is not cost-effective?

--
A language that doesn't affect the way
you think about programming is
not worth knowing.
Alan Perlis
  #12  
Old December 11th 07, 03:19 PM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
Robert Redelmeier
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Posts: 316
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

In comp.sys.ibm.pc.hardware.chips wrote in part:
SRAM could shave off 15 ns in the case of DRAM page miss. Or
50-55ns in the case of page conflict, but those are very
rare. In the supposedly most common case of DRAM page hit
SRAM doesn't help at all. Actually, you will have hard
time finding commodity SRAMs that is as fast as now common
DDR2-800 CL5 at page hit.


You are talking device response times, and I appreciate your
information. However, I am interested in system response (software
performance), and my measurements are far less encouraging:

Latency CPU@MHz mem.ctl RAM
ns

88 k8@2000 NForce3 DDR400
144 P3@1000 laptop SO-PC133?
148 2*P3@860 Serverworks ??
178 P4@1800 i850 RDRAM
184 K7@1667 SiS735 PC133
185 P3@600 440BX PC100
217 2*Cel@500 440BX PC90
234 P2@350 440BX PC100?
288 P2@333 440BX PC66

I do need to find & test some more modern systems, but I'm
underwhelmed by the slowness of latency improvement. CPU has
increased min 4x, latency response at best 2.5x . Run this
pgm from L2 (small set) and it comes back around 10 ns.



compile: $ gcc -O2 lat10m.c
run: $ time ./a.out [multiply user time by 100 to give ns]

/* lat10m.c - Measure latency of 10 million fresh memory reads
(C) Copyright 2005 Robert Redelmeier - GPL v2.0 licence granted */
int p[ 121 ] ;
main (void) {
int i, j ;
for ( i=0 ; i 121 ; i++ ) p[i] = 0x1FFFFF & (i-5000) ;
for ( j=i=0 ; i 9600000 ; i++ ) j = p[j] ;
return j ; }


-- Robert







 




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