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Rambus aims for 1 TeraByte per second memory bandwidth by 2010



 
 
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  #1  
Old December 4th 07, 05:48 AM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
daytripper
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Posts: 265
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

On Mon, 3 Dec 2007 21:38:28 -0800 (PST), David Kanter
wrote:

Have you ever heard of copyright infringement? Because you just
posted my article without attribution, and you have no rights to
reprint or re-use my article.

DK


Ever hear of the "Fair Use Doctrine"? If not, you really ought to become
familiar with it. It clearly covers his ass quite well.

He *did* post a link to the original article, so it was obvious he wasn't
trying to claim originality.

It was clearly stupid of him to paste the content here when the link would
have sufficed - a senseless waste of bytes (Oh! The humanity!) but the
omission of full attribution here is a hand-slappable offense, nothing more...

/daytripper
  #2  
Old December 4th 07, 07:03 AM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
Terje Mathisen
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Posts: 39
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

daytripper wrote:
On Mon, 3 Dec 2007 21:38:28 -0800 (PST), David Kanter
wrote:

Have you ever heard of copyright infringement? Because you just
posted my article without attribution, and you have no rights to
reprint or re-use my article.

DK


Ever hear of the "Fair Use Doctrine"? If not, you really ought to become
familiar with it. It clearly covers his ass quite well.


Not "quite well" IMHO.

Posting the link plus a short excerpt would have been fine, as it is
David possibly lost a _lot_ of page views which would have generated
real income for him.


He *did* post a link to the original article, so it was obvious he wasn't
trying to claim originality.

It was clearly stupid of him to paste the content here when the link would
have sufficed - a senseless waste of bytes (Oh! The humanity!) but the
omission of full attribution here is a hand-slappable offense, nothing more...


Consider him slapped then.

Terje

--
-
"almost all programming can be viewed as an exercise in caching"
  #3  
Old December 4th 07, 07:17 AM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
Chris Thomasson
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Posts: 28
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

"Terje Mathisen" wrote in message
...
daytripper wrote:
On Mon, 3 Dec 2007 21:38:28 -0800 (PST), David Kanter
wrote:

Have you ever heard of copyright infringement? Because you just
posted my article without attribution, and you have no rights to
reprint or re-use my article.

DK


Ever hear of the "Fair Use Doctrine"? If not, you really ought to become
familiar with it. It clearly covers his ass quite well.


Not "quite well" IMHO.

Posting the link plus a short excerpt would have been fine, as it is David
possibly lost a _lot_ of page views which would have generated real income
for him.


[...]

Good point.

  #4  
Old December 4th 07, 10:11 PM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
Del Cecchi
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Posts: 84
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010


"Chris Thomasson" wrote in message
. ..
"Terje Mathisen" wrote in message
...
daytripper wrote:
On Mon, 3 Dec 2007 21:38:28 -0800 (PST), David Kanter

wrote:

Have you ever heard of copyright infringement? Because you just
posted my article without attribution, and you have no rights to
reprint or re-use my article.

DK

Ever hear of the "Fair Use Doctrine"? If not, you really ought to
become
familiar with it. It clearly covers his ass quite well.


Not "quite well" IMHO.

Posting the link plus a short excerpt would have been fine, as it is
David possibly lost a _lot_ of page views which would have generated
real income for him.


[...]

Good point.

So I went and clicked on the link. I hope that helps.


  #5  
Old December 5th 07, 05:31 AM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
daytripper
external usenet poster
 
Posts: 265
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

On Tue, 04 Dec 2007 08:03:36 +0100, Terje Mathisen
wrote:

daytripper wrote:
On Mon, 3 Dec 2007 21:38:28 -0800 (PST), David Kanter
wrote:

Have you ever heard of copyright infringement? Because you just
posted my article without attribution, and you have no rights to
reprint or re-use my article.

DK


Ever hear of the "Fair Use Doctrine"? If not, you really ought to become
familiar with it. It clearly covers his ass quite well.


Not "quite well" IMHO.

Posting the link plus a short excerpt would have been fine, as it is
David possibly lost a _lot_ of page views which would have generated
real income for him.


Ah - I thought this was a legal/ethical issue and not a financial one...

If it helps, I had immediately forwarded - *just the link* - to my buddies on
the Jedec memory subgroup meeting in Hawaii this week. What with all the rain
keeping them off the golf courses they should have plenty of time to click
through ;-)

Of course, the first question they had was "what about latency?"

/daytripper
  #6  
Old December 6th 07, 05:03 AM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
The little lost angel
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Posts: 210
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

On Wed, 05 Dec 2007 00:31:25 -0500, daytripper
wrote:

On Tue, 04 Dec 2007 08:03:36 +0100, Terje Mathisen
wrote:
Posting the link plus a short excerpt would have been fine, as it is
David possibly lost a _lot_ of page views which would have generated
real income for him.


Ah - I thought this was a legal/ethical issue and not a financial one...


Copyrights, as it is, is essentially a financially motivated legal
issue, isn't? Otherwise, somebody ought to explain to certain large
groups busy harrassing/suing young children and single parents about
having ethics.

--
A Lost Angel, fallen from heaven
Lost in dreams, Lost in aspirations,
Lost to the world, Lost to myself
  #7  
Old December 7th 07, 02:47 PM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
Robert Redelmeier
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Posts: 316
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

In comp.sys.ibm.pc.hardware.chips Robert Myers wrote in part:
On Dec 5, 12:31 am, daytripper wrote
Of course, the first question they had was "what about latency?"


Bandwidth is king. Said it long ago. Wider is the only


Uhm, err, for what sorts of problems/tasks? Had bandwidth
been always and overall governing, Rambus first iteration
would have succeeded. Their execs obviously thought they
had technical advantages worth the commercial conditions.
The market disagreed.

way left to go. We will see more and more of same and the
only thing to do about latency is to hide it.


This has often been tried with only partial success (video)
Sometimes latency governs and cannot be hidden (databases).
It must be reduced as AMD has done fairly successfully.

-- Robert

  #8  
Old December 7th 07, 10:51 PM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
daytripper
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Posts: 265
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

On Fri, 7 Dec 2007 12:49:09 -0800 (PST), Robert Myers
wrote:

On Dec 7, 9:47 am, Robert Redelmeier wrote:
In comp.sys.ibm.pc.hardware.chips Robert Myers wrote in part:

On Dec 5, 12:31 am, daytripper wrote
Of course, the first question they had was "what about latency?"


Bandwidth is king. Said it long ago. Wider is the only


Uhm, err, for what sorts of problems/tasks? Had bandwidth
been always and overall governing, Rambus first iteration
would have succeeded. Their execs obviously thought they
had technical advantages worth the commercial conditions.
The market disagreed.

Rambus was hot and expensive.

To turn your argument over, if latency were king, Intel would be out
of business and/or have changed tactics drastically. Intel has taken
its own sweet time about moving away from its traditional memory
architecture and seems to be doing quite nicely.

way left to go. We will see more and more of same and the
only thing to do about latency is to hide it.


This has often been tried with only partial success (video)
Sometimes latency governs and cannot be hidden (databases).
It must be reduced as AMD has done fairly successfully.

That's a one-time gain that has been known to be available at least
since the last editions of alpha. For latency, there is nowhere left
to go in terms of completely unpredictable reads from memory (or
disk). All the tactics that work (prefetch, hide, cache) depend on
the ability to foresee the future, another hobby horse of mine. Terje
might claim that improvements come from cache management.
Improvements in cache management come from more successfully
exploiting nonrandomness; that is to say, the ability to predict the
future.

Robert.


So, in short, you don't think the biggest problem confronting processor design
and performance isn't important because "it's hard"...

/daytripper (well, that's one way to go, I guess ;-)
  #9  
Old December 8th 07, 07:18 AM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
Robert Redelmeier
external usenet poster
 
Posts: 316
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

In comp.sys.ibm.pc.hardware.chips Robert Myers wrote in part:
To turn your argument over, if latency were king, Intel would be
out of business and/or have changed tactics drastically. Intel has
taken its own sweet time about moving away from its traditional
memory architecture and seems to be doing quite nicely.


Your argument assumes Intel and AMD are identicial with respect
to market success. They are NOT! Intel is much larger and can
afford many mistakes. AMD's production capacity is too small to
be any sort of real threat, at least in the short and medium term.

That's a one-time gain that has been known to be available at
least since the last editions of alpha.


Sure. But why not grab it?

For latency, there is nowhere left to go in terms of
completely unpredictable reads from memory (or disk).


Sure there is -- SRAM and other designs which take more xtors
per cell. With the continually decreasing marginal cost
of xtors and a shortage of useful things to do with them,
I expect this transition to happen at some point.

All the tactics that work (prefetch, hide, cache) depend
on the ability to foresee the future, another hobby horse
of mine. Terje might claim that improvements come from
cache management. Improvements in cache management come
from more successfully exploiting nonrandomness; that is
to say, the ability to predict the future.


I agree with Terje and those things can be done in
addition to debottlenecking the circuit response.

-- Robert

  #10  
Old December 10th 07, 10:31 AM posted to comp.arch.embedded,comp.arch,comp.sys.ibm.pc.hardware.chips,alt.comp.hardware.amd.x86-64,comp.sys.intel
Ken Hagan
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Posts: 12
Default Rambus aims for 1 TeraByte per second memory bandwidth by 2010

On Fri, 07 Dec 2007 22:51:06 -0000, daytripper
wrote:

So, in short, you don't think the biggest problem confronting processor
design and performance isn't important because "it's hard"...

/daytripper (well, that's one way to go, I guess ;-)


I dunno if its a fair summary of Robert's position, but it is a fair
piece of strategy. It is silly to try to solve an impossible problem.
It is almost as silly to try to solve an almost impossible problem.
 




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