Gaming AMD vs Intel

On Wed, 07 Sep 2005 16:48:31 +0000, Felger Carbon wrote:

"Wes Newell" wrote in message
newsan.2005.09.07.06.03.43.197405@TAKEOUTverizon .net...
On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side
cache bus"
of the P6. The P5 had no "FSB".

Under your definition of FSB, then no AMD CPU's have ever had a FSB.
Let's
see just how many people you can convince of that.:-)

Wes, are you saying no AMD chip ever had an L2 cache hung off the back
of the CPU? Wow, is _my_ memory ever going south! ;-)

Well, that's was what I said, but I wasn't thinking back past the K7 and
K8's, and I actually never paid much attention to what they called the
bus to the earlier cpu's that had cache on the MB. Was that an L2 cache? I
thought it was L1. Too long ago to remember and I'm too lazy to look it up.:-)
And I just remembered that the Slot A k7's had it's L2 cache on the cpu
board too, and not in the cpu die, but I don't recall AMD or anyone else
using back side bus for it.

--
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On Wed, 07 Sep 2005 18:57:23 +0000, Wes Newell wrote:

On Wed, 07 Sep 2005 16:48:31 +0000, Felger Carbon wrote:

"Wes Newell" wrote in message
newsan.2005.09.07.06.03.43.197405@TAKEOUTverizon .net...
On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side
cache bus"
of the P6. The P5 had no "FSB".

Under your definition of FSB, then no AMD CPU's have ever had a FSB.
Let's
see just how many people you can convince of that.:-)

Wes, are you saying no AMD chip ever had an L2 cache hung off the back
of the CPU? Wow, is _my_ memory ever going south! ;-)

Well, that's was what I said, but I wasn't thinking back past the K7 and
K8's, and I actually never paid much attention to what they called the
bus to the earlier cpu's that had cache on the MB.

K7s had the L2 on the "back side". It wasn't hooked into the external
bus, as was socket-7 (and before).

Was that an L2 cache? I thought it was L1.

Modern processors have *long* had seperate I and D L1s, burried in the
instruction-fetch and load-store elements. The K7s L2 is certainly hung
off the "back-side", meaning not connected to the system bus. The K8
further seperates the I/O and memory busses, so there is no longer
soethign even resembling a "front-side bus". There is (are) memory
bus(ses) and HT link(s). Alghough, the HT link isn't just an I/O bus. It
also crries coherency information (but I/O must be cache coherent too).

Too long ago to remember and
I'm too lazy to look it up.:-) And I just remembered that the Slot A
k7's had it's L2 cache on the cpu board too, and not in the cpu die, but
I don't recall AMD or anyone else using back side bus for it.

I'm from Missouri (close, but not really). I never remember a slot-A K7
with on-board L2. Even the K6-III has an on-chip L2, but allows an
on-board L3 (mine has a 2MB L3).

--
Keith

On Wed, 07 Sep 2005 16:53:57 -0500, Ed wrote:

On Wed, 07 Sep 2005 16:42:58 -0400, keith wrote:



I'm from Missouri (close, but not really). I never remember a slot-A K7
with on-board L2. Even the K6-III has an on-chip L2, but allows an
on-board L3 (mine has a 2MB L3).

Slot-A didn't have on-die L2 cache.

I didn't say it did. Note that the Slot-1 PII didn't have an integrated
cache either, but the cache was still on the "back side" of the chip. The
Slot-A K7 was no different.

K7-500 512K L2 (has a 650Mhz core)
http://img9.imageshack.us/img9/6074/k7500650core0ch.jpg

Sheesh, learn *SOMETHING*! Do start with reading comprehension.

--
Keith

On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
wrote:

On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side cache bus"
of the P6. The P5 had no "FSB".

Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
see just how many people you can convince of that.:-)

Not true at all. The original AMD Athlon had both a front-side bus,
connecting the CPU to the chipset, I/O and memory, and a backside bus
that connected the CPU to the cache chips on the Slot-A cartridge.
This was actually the last x86 CPU that I'm aware of which did have a
frontside bus (Intel had already gone to integrated cache by this
time).

Of course, the EV6 bus used to connect Athlon CPUs to their chipsets
is only kinda-sorta a bus in itself. Really it's more of a
point-to-point link, though it's in that fuzzy area that blurs the
lines between the two a bit (where the GTL+ bus used in the P6 is
definitely a bus and Hypertransport is definitely not a bus, EV6 falls
somewhere in between).

While the term may have originated the way you say, it was then later used
to indicate the connection between the CPU and the chipset.

Yes, a lot of people incorrectly refer to the a connection between the
CPU and the chipset as a "Front Side Bus". Just because lots of
people make a mistake that doesn't mean that they are right.

People also still call the memory controller the "northbridge" and the
I/O chip a "southbridge", which also makes no sense given that they
are no longer being connected via PCI and they usually aren't bridges
at all. Again, just because people incorrectly use a term doesn't
make it correct.

Now, that same
connection is the HT link of the K8. So it only makes sense to use the
same terminology for the very specific connection even though memory data
now has own single use bus for the memory.

It doesn't make any sense with the AthlonXP or the P4 and it makes
MUCH less sense with the Athlon64/Opteron. Just because it's a common
mistake doesn't make it any less of a mistake.

The FSB still carries all other
IO operations to/from the system. Once they move all this into the CPU,
there will no longer be a FSB. Until then, a duck by any other name is
still a duck.

Yes, but that still doesn't make a goose a duck, even if lots of
people mix the two of them up.

FSB doesn't describe it's function at all. What's the "back side" of
the HT link?

What HT link? Ht links are used everywhere. AFAIK, they don't need a
backside.

The point is that you can't have a "front side bus" unless you have a
corresponding "back side bus". Hypertransport does not have such a
corresponding back side so therefore it's not the "front side" of
anything.

Given that it's not the 'front side' of anything and, as others have
mentioned, it's not a 'bus' at all then it DEFINITELY is not a "Front
Side Bus".

They function fully indepentant of other buses. If I assume you
are talking about the HT link used to connect the K8 cpu's to the chipset,
I'd just answer that it's in the same place as back side of the K7 CPU's
FSB. You're really digging a hole for yourself here.

The original Athlon had a backside bus with to the cache chips on the
cartridge. This was later removed with the "Thunderbird" chips with
integrated cache. As such, from the "Thunderbird" on forward
(including all AthlonXP chips) there was no FSB on the AthlonXP. Same
goes for the PIII from the "Coppermine" onwards as well as ALL P4
chips. None of those have FSBs, despite the fact that many people
incorrectly use the term to describe the system bus of said chips.

IOW's using the term FSB
specifically refers to the connection between the CPU and chipset,

No, it doesn't. I specifically refers to the fact that the caches are on
the other side (back side) of the P6 memory bus. That architecture was
around for a while, so it stuck. There was no "FSB" in the P5
architecture. It's an invention of the P6 and should stay there, since
it no longer describes any function.

Why are you stuck on the Pentium Pro. FSB has been used for years to
indicate the connection between the CPU and the chipset.

The term "Front Side Bus" was never used with the Pentium chips
because there was only one bus. FSB came into computer use with the
PentiumPro where Intel introduced a chip with a Frontside Bus
(connecting to main memory and I/O) and a Backside bus (connecting to
cache). The terminology continued through the PII and early PIII
chips, as well as early Athlon chips, as they had two buses, one for
memory and I/O and the other for cache. For chips with only a single
bus the term "FSB" makes no sense. Never has and never will, no
matter how many people make such a mistake.

With the Athlon64 and Opteron it's just more obviously incorrect than
it is with the AthlonXP and P4 chips.

while
using the term HT link could be any of many different type of
connections an HT link is used for since it's used in many more
applications than just a FSB. Some refer to the bus as a system bus,

"System bus" works for me. I/O bus makes more sense.

Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
buses. So how are you going to distinquish which one you are talking about
if you just use system bus? Damn, I wonder if FSB would do that?:-)
I/O bus. Ditto, and you can throw HTlink into the mix too since it is also
an I/O bus.

Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
point-to-point link. PCI-E and AGP are also definitely not buses,
though I expect many people to incorrectly call them such. PCI and
ISA are buses

-------------
Tony Hill
hilla underscore 20 at yahoo dot ca

On Wed, 07 Sep 2005 16:42:58 -0400, keith wrote:
Too long ago to remember and
I'm too lazy to look it up.:-) And I just remembered that the Slot A
k7's had it's L2 cache on the cpu board too, and not in the cpu die, but
I don't recall AMD or anyone else using back side bus for it.

I'm from Missouri (close, but not really). I never remember a slot-A K7
with on-board L2.

There were a *few* Slot-A K7 chips that had integrated L2, but they
were only released for compatibility purposes (much like what Intel
did with some of their later Slot-1 PIII chips, though AMD released
far fewer of such chips). You might even be able to find someone
still selling such a beast if you look hard enough, just do a search
for "Thunderbird Slot-A".

-------------
Tony Hill
hilla underscore 20 at yahoo dot ca

On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:

On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
wrote:

On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side cache bus"
of the P6. The P5 had no "FSB".

Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
see just how many people you can convince of that.:-)

Not true at all. The original AMD Athlon had both a front-side bus,
connecting the CPU to the chipset, I/O and memory, and a backside bus
that connected the CPU to the cache chips on the Slot-A cartridge.
This was actually the last x86 CPU that I'm aware of which did have a
frontside bus (Intel had already gone to integrated cache by this
time).

You're partially right anyway.:-)

Of course, the EV6 bus used to connect Athlon CPUs to their chipsets
is only kinda-sorta a bus in itself. Really it's more of a
point-to-point link, though it's in that fuzzy area that blurs the
lines between the two a bit (where the GTL+ bus used in the P6 is
definitely a bus and Hypertransport is definitely not a bus, EV6 falls
somewhere in between).

You're out to lunch here for the most part.

While the term may have originated the way you say, it was then later
used to indicate the connection between the CPU and the chipset.

Yes, a lot of people incorrectly refer to the a connection between the
CPU and the chipset as a "Front Side Bus". Just because lots of people
make a mistake that doesn't mean that they are right.

Wrong. FSB is defined as the bus connection between the CPU and chipset.
AMD calls the bus a FSB and I'm pretty sure Intel did too on the P4. If
you break down the term, it's pretty simple. Front side, meaning not the
back side, and bus. A bus is a collection of 1 or more electrical
connections between 2 or more points. The type of bus (standard, EV6, HT
link, or any other type) is of no concern.

People also still call the memory controller the "northbridge" and the
I/O chip a "southbridge", which also makes no sense given that they are
no longer being connected via PCI and they usually aren't bridges at
all. Again, just because people incorrectly use a term doesn't make it
correct.

What? The northbridge has much more in it than just a memory controller.
And the K8 northbridge doesn't even have a memory controller in it.

Now, that same
connection is the HT link of the K8. So it only makes sense to use the
same terminology for the very specific connection even though memory
data now has own single use bus for the memory.

It doesn't make any sense with the AthlonXP or the P4 and it makes MUCH
less sense with the Athlon64/Opteron. Just because it's a common
mistake doesn't make it any less of a mistake.

Well, AMD and Intel disagree, as do I. ANd it's used for one purpose IMO,
to distinquish which fricking bus you are talking about.

The FSB still carries all other
IO operations to/from the system. Once they move all this into the CPU,
there will no longer be a FSB. Until then, a duck by any other name is
still a duck.

Yes, but that still doesn't make a goose a duck, even if lots of people
mix the two of them up.

Just out of curiosty, I'd like you to tell me what the name of the bus
is between the CPU and the chipset. And I don't mean what type of bus.
It's already known to be an HT link. So what's the name you want to give
it so that when someone refers to it by that name they will know exactly
which bus you are talking about and where it connects. And it has to be
specific. Sytem bus doesn't cut, there's many system buses. CPU bus
doesn't cut it as there are many cpu busses if you count the internal
busses. I say FSB. I'm waiting for a better one from you.


The point is that you can't have a "front side bus" unless you have a
corresponding "back side bus". Hypertransport does not have such a
corresponding back side so therefore it's not the "front side" of
anything.

I'll give you two options. Take your pick. (1) The internal bus to the L2
cache is the back side bus. It just internal now. (2) Why must there be a
BSB at all? FSB is more of a designation for a certain bus rather than
actually describing it's location. It connects between the CPU and
chipset, just as it did on the Athlon (non 64) cpu's. And no one had any
complaints of calling it a FSB then. That's what AMD called it.

They function fully indepentant of other buses. If I assume you
are talking about the HT link used to connect the K8 cpu's to the
chipset, I'd just answer that it's in the same place as back side of the
K7 CPU's FSB. You're really digging a hole for yourself here.

The original Athlon had a backside bus with to the cache chips on the
cartridge. This was later removed with the "Thunderbird" chips with
integrated cache. As such, from the "Thunderbird" on forward (including
all AthlonXP chips) there was no FSB on the AthlonXP.

They didn't remove the L2 cache. It was just moved inside the die. You
think that memory just magically connects to the rest of the CPU without
a bus. I sure as hell wish I'd known I could do that when I was designing
memory controllers.:-)

Same goes for the
PIII from the "Coppermine" onwards as well as ALL P4 chips. None of
those have FSBs, despite the fact that many people incorrectly use the
term to describe the system bus of said chips.

I'm not an Intel user, but I assume you are as wrong about this as you are
about the AMD's not having a FSB.

Why are you stuck on the Pentium Pro. FSB has been used for years to
indicate the connection between the CPU and the chipset.

The term "Front Side Bus" was never used with the Pentium chips because
there was only one bus. FSB came into computer use with the PentiumPro
where Intel introduced a chip with a Frontside Bus (connecting to main
memory and I/O) and a Backside bus (connecting to cache).

How many times must you guys write this? No one argues that point.

The terminology continued through the PII and early PIII chips, as well
as early Athlon chips, as they had two buses, one for memory and I/O
and the other for cache. For chips with only a single bus the term "FSB"
makes no sense. Never has and never will, no matter how many people
make such a mistake.

It makes all the sense in the world defined as the connection between the
CPU and chipset. If not, tell me what does. All you people have said it's
not right, yet none of you have come up with a definitive name for the
bus. I wonder if that's why it's stuck around so long, since I've seen it
defined as just that, the bus between the CPU and chipset.

With the Athlon64 and Opteron it's just more obviously incorrect than it
is with the AthlonXP and P4 chips.

Tell AMD and Intel, they need some humor too.

Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
point-to-point link. PCI-E and AGP are also definitely not buses,
though I expect many people to incorrectly call them such. PCI and ISA
are buses

I don't know what you think a bus is. perhaps you should give your
definition of a bus, and not a school bus. Every definition of bus I've
seen says it an electrical pathway. So unless the HT link works without
electricty, it's a bus. As are all the others you claim aren't.

And now the killer punch. From;

http://www.hypertransport.org/consortium/cons_faqs.cfm

9. How does HyperTransport technology compare to other bus technologies?

As compared to older multidrop, shared buses such as PCI, PCI-X or SysAD,
HyperTransport provides a far simplier electrical interface, but with much
greater bandwidth. Instead of a wide, address/data/control multidrop,
shared bus such as implemented by PCI, PCI-X or SysAD technologies,
HyperTransport deploys narrow, but very fast unidirectional links to carry
both data and command information encoded into packets. Unidirectional
links provide significantly better signal integrity at high speeds and
enable much faster data transfers with low-power 1.2V LVDS signals. In
addition, link widths can be asymmetrical, meaning that 2 bit wide links
can easily connect to 8 bit wide links and 8 bit wide links can connect to
16 or 32 bit wide links and so on. Thus, the HyperTransport Technology
eliminates the problems associated with high speed parallel buses with
their many noisy bus signals (multiplexed data/address, and clock and
control signals) while providing scalable bandwidth wherever it is needed
in the system. As compared to newer serial I/O technologies such as
RapidIO and PCI Express, HyperTransport shares some raw bandwidth
characteristics, but is significantly different in some key
characteristics.
*****Read this pargraph carefully********
HyperTransport was designed to support both CPU-to-CPU
communications as well as CPU-to-I/O transfers, thus, it features very low
latency. Consequently, it has been incorporated into multiple x86 and MIPS
architecture processors as an integrated front-side bus.
*And don't miss this................................. ^^^^^^^^^ *

Serial technologies such as PCI Express and RapidIO require
serial-deserializer interfaces and have the burden of extensive overhead
in encoding parallel data into serial data, embedding clock information,
re-acquiring and decoding the data stream. The parallel technology of
HyperTransport needs no serdes and clock encoding overhead making it far
more efficient in data transfers.

I rest my case.;-)

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
Verizon server http://mysite.verizon.net/res0exft/cpu.htm

Wes Newell wrote:
*
snip

Serial technologies such as PCI Express and RapidIO require
serial-deserializer interfaces and have the burden of extensive overhead
in encoding parallel data into serial data, embedding clock information,
re-acquiring and decoding the data stream. The parallel technology of
HyperTransport needs no serdes and clock encoding overhead making it far
more efficient in data transfers.

I rest my case.;-)


The last paragraph you quote, shown above, is Clintonian at best, with
respect to comparing the physical aspects of HT and PCI-E.

--
Del Cecchi
"This post is my own and doesn’t necessarily represent IBM’s positions,
strategies or opinions.”

On Thu, 08 Sep 2005 21:41:36 -0400, Tony Hill wrote:

On Wed, 07 Sep 2005 16:42:58 -0400, keith wrote:
Too long ago to remember and
I'm too lazy to look it up.:-) And I just remembered that the Slot A
k7's had it's L2 cache on the cpu board too, and not in the cpu die, but
I don't recall AMD or anyone else using back side bus for it.

I'm from Missouri (close, but not really). I never remember a slot-A K7
with on-board L2.

There were a *few* Slot-A K7 chips that had integrated L2, but they
were only released for compatibility purposes (much like what Intel
did with some of their later Slot-1 PIII chips, though AMD released
far fewer of such chips). You might even be able to find someone
still selling such a beast if you look hard enough, just do a search
for "Thunderbird Slot-A".

I meant the cache on the board (system bus), as opposed to "integrated"
or on the cartridge (on the "back-side").

--
Keith

On Thu, 08 Sep 2005 21:41:35 -0400, Tony Hill wrote:

On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
wrote:

On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side cache bus"
of the P6. The P5 had no "FSB".

Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
see just how many people you can convince of that.:-)

Not true at all. The original AMD Athlon had both a front-side bus,
connecting the CPU to the chipset, I/O and memory, and a backside bus
that connected the CPU to the cache chips on the Slot-A cartridge.
This was actually the last x86 CPU that I'm aware of which did have a
frontside bus (Intel had already gone to integrated cache by this
time).

Just because the cache is integrated doesn't mean the cache isn't on the
"back side" of the processor. The "back-side" concept was really a
separation of the cache from the memory busses.

Of course, the EV6 bus used to connect Athlon CPUs to their chipsets is
only kinda-sorta a bus in itself. Really it's more of a point-to-point
link, though it's in that fuzzy area that blurs the lines between the
two a bit (where the GTL+ bus used in the P6 is definitely a bus and
Hypertransport is definitely not a bus, EV6 falls somewhere in between).

Works for me.

While the term may have originated the way you say, it was then later
used to indicate the connection between the CPU and the chipset.

Yes, a lot of people incorrectly refer to the a connection between the
CPU and the chipset as a "Front Side Bus". Just because lots of people
make a mistake that doesn't mean that they are right.

Yep! It ignores the reason it was called the "front-side bus" to begin
with.

People also still call the memory controller the "northbridge" and the
I/O chip a "southbridge", which also makes no sense given that they are
no longer being connected via PCI and they usually aren't bridges at
all. Again, just because people incorrectly use a term doesn't make it
correct.

As long as there is an off-chip memory controller and high-speed
peripherals on the "bridge", it's proper to call it a "north-bridge". If
there is a low-spped bridge hanging off that, "south-bridge" is a useful
concept.

Now, that same
connection is the HT link of the K8. So it only makes sense to use the
same terminology for the very specific connection even though memory
data now has own single use bus for the memory.

It doesn't make any sense with the AthlonXP or the P4 and it makes MUCH
less sense with the Athlon64/Opteron. Just because it's a common
mistake doesn't make it any less of a mistake.

Why doesn't "front-side bus" work with the P4 or K7? The cache is still
on the "back side" of the processor, even though it's on the chip.

snip

They function fully indepentant of other buses. If I assume you
are talking about the HT link used to connect the K8 cpu's to the
chipset, I'd just answer that it's in the same place as back side of the
K7 CPU's FSB. You're really digging a hole for yourself here.

The original Athlon had a backside bus with to the cache chips on the
cartridge. This was later removed with the "Thunderbird" chips with
integrated cache. As such, from the "Thunderbird" on forward (including
all AthlonXP chips) there was no FSB on the AthlonXP. Same goes for the
PIII from the "Coppermine" onwards as well as ALL P4 chips. None of
those have FSBs, despite the fact that many people incorrectly use the
term to describe the system bus of said chips.

No, the back side bus wasn't removed. It was integrated onto the chip.
The architecture is the same, if the parts moved around.

IOW's using the term FSB
specifically refers to the connection between the CPU and chipset,

No, it doesn't. I specifically refers to the fact that the caches are
on the other side (back side) of the P6 memory bus. That architecture
was around for a while, so it stuck. There was no "FSB" in the P5
architecture. It's an invention of the P6 and should stay there,
since it no longer describes any function.

Why are you stuck on the Pentium Pro. FSB has been used for years to
indicate the connection between the CPU and the chipset.

The term "Front Side Bus" was never used with the Pentium chips because
there was only one bus. FSB came into computer use with the PentiumPro
where Intel introduced a chip with a Frontside Bus (connecting to main
memory and I/O) and a Backside bus (connecting to cache). The
terminology continued through the PII and early PIII chips, as well as
early Athlon chips, as they had two buses, one for memory and I/O and
the other for cache. For chips with only a single bus the term "FSB"
makes no sense. Never has and never will, no matter how many people
make such a mistake.

I dissagree. The back-side bus was integrated onto the chip. Again, the
memory architecture was the same.

With the Athlon64 and Opteron it's just more obviously incorrect than it
is with the AthlonXP and P4 chips.

It *is* incorrect, not so with the P4 or K7.

while
using the term HT link could be any of many different type of
connections an HT link is used for since it's used in many more
applications than just a FSB. Some refer to the bus as a system bus,

"System bus" works for me. I/O bus makes more sense.

Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
buses. So how are you going to distinquish which one you are talking
about if you just use system bus? Damn, I wonder if FSB would do
that?:-) I/O bus. Ditto, and you can throw HTlink into the mix too since
it is also an I/O bus.

Hypertransport is NOT an 'bus' in any way, shape or form. HT is a
point-to-point link. PCI-E and AGP are also definitely not buses,
though I expect many people to incorrectly call them such. PCI and ISA
are buses

True enough. Apparently some people call ducks geese too. ;-)

--
Keith

On Fri, 09 Sep 2005 10:01:26 -0500, Del Cecchi wrote:

Wes Newell wrote:
*
snip

Serial technologies such as PCI Express and RapidIO require
serial-deserializer interfaces and have the burden of extensive overhead
in encoding parallel data into serial data, embedding clock information,
re-acquiring and decoding the data stream. The parallel technology of
HyperTransport needs no serdes and clock encoding overhead making it far
more efficient in data transfers.

I rest my case.;-)


The last paragraph you quote, shown above, is Clintonian at best, with
respect to comparing the physical aspects of HT and PCI-E.

You snipped the portion I had highlighted. I didn't even read this part.
Nor do I have any comments on it. If you have a problem with it. i suggest
you contact the people that wrote it. If Clintonian refers to refers to
our lying crooked x pres, those are are fighting words. I never voted for
the lowlife.

--
KT133 MB, CPU @2400MHz (24x100): SIS755 MB CPU @2330MHz (10x233)
Need good help? Provide all system info with question.
My server http://wesnewell.no-ip.com/cpu.php
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