Gaming AMD vs Intel

On Tue, 06 Sep 2005 06:14:02 GMT, Wes Newell
wrote:

On Mon, 05 Sep 2005 16:22:51 -0700, YKhan wrote:

not only improve the design of chips, but it actually redesign some
very basic concepts of its chips. One example is that the ubiquitous
front-side bus (FSB), namely AMD got rid of it! The FSB was the method
by which PC chips had connected to their peripheral devices and its
memory ever since the first 8088 IBM PC-XT. AMD threw out the FSB, and
replaced it with two seperate connections, one for the memory and one
for the peripherals.

For clearity, AMD didn't get rid of the FSB, they just stopped calling it
a FSB, even though that's what it still is, by definition.

The term FSB came about with Intel's Pentium Pro, where the dual chip
CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
- L2 cache data as well as I/O and memory transfers. By definition, a
FSB carried all CPU-memory and CPU-I/O transfers... but not CPU-L2
cache transfers. To me calling AMD's HT a FSB is about as valid as
continuing to use North Bridge & South Bridge for the two chips normally
used in a chipset - it's not really applicable any more but people will say
it as a convenience term

They did
however move the memory controller onto the cpu, so that ram data now has
it's own data path to the CPU. This move, and not the move to an HT link
for the FSB is where the major performance gain was made. With the move to
the seperate memory bus, the FSB (now a serial HT link, instead of a
paralell bus) speed is of little importance.

As recently discussed here, HyperTransport is not a serial bus - it *is*
packetized and it is point-to-point/uni-directional but each byte-width
path has a separate clock signal and the chip/system designers have to pay
close attention to clock skew.

As far as speed, with current Athlon64 systems, the 2-byte-wide down-link
from CPU-chipset-PCI-e(x16) is, in theory, maxed out at the 1GHz clock
rate. Put another way, the current PCI-e x16 graphics path has a max
bandwidth of 4.1GB/s; the HT down-link has a max bandwidth of 4GB/s so in
theory, at least, it would be possible for memory-graphics transfers to
saturate the HT down-link.

I don't think this is a problem for the moment but add in that the 4GB/s HT
up-link for an integrated graphics chipset could be seriously stressed and
cause HT traffic contention, it could lead to problems down the road... as
well as supply ammo to anti-AMD marketing efforts. So yes, speed of HT is
an issue and the integrated PCI-e that AMD is adding will help mitigate
those err, concerns.

--
Rgds, George Macdonald

Or, if your pockets allow for it, go for dual
dual-core Opteron, making it a quad. Maybe today's games can't take
real advantage of multithreading, but I bet the games of tomorrow (and
not only games) are already being coded to use multiple cores to their
advantage.

Forgive me, I have not read much about Opteron chips. Are you saying
a system with dual 64 bit Opteron chips is about the same as what a
QUAD A64 X2 would be ?

wrote:
Or, if your pockets allow for it, go for dual
dual-core Opteron, making it a quad. Maybe today's games can't take
real advantage of multithreading, but I bet the games of tomorrow (and
not only games) are already being coded to use multiple cores to their
advantage.

Forgive me, I have not read much about Opteron chips. Are you saying
a system with dual 64 bit Opteron chips is about the same as what a
QUAD A64 X2 would be ?

No, A64 systems are limited to one and only one CPU socket. So if you
have a dual-core A64, then that's all you're ever going to get: two
cores. However, Opteron workstations often have dual sockets, and
dual-core Opterons in each socket will mean that you have upto four
cores.

Yousuf Khan

To me, a bus would be a multi-drop access medium, with multiple devices
(including CPUs) all sharing a single data path between each other.
Hypertransport is a point-to-point interface, you can only connect to
one other device with each HT link. This would be much the same as old
collision-based Ethernet vs. switched Ethernet.

Yousuf Khan

On Tue, 06 Sep 2005 06:09:35 -0400, George Macdonald wrote:

For clearity, AMD didn't get rid of the FSB, they just stopped calling it
a FSB, even though that's what it still is, by definition.

The term FSB came about with Intel's Pentium Pro, where the dual chip
CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
- L2 cache data as well as I/O and memory transfers. By definition, a
FSB carried all CPU-memory and CPU-I/O transfers... but not CPU-L2
cache transfers. To me calling AMD's HT a FSB is about as valid as
continuing to use North Bridge & South Bridge for the two chips normally
used in a chipset - it's not really applicable any more but people will say
it as a convenience term

FSB by definition connects the CPU to the chipset. HT link by definition
is just that, any bus using HT technolog and is not limited to
connections between a cpu and a chipset. So given the choice of
calling the bus a FSB, or the HT link, FSB fits the bill while HT link
only describes the type of bus, not the bus itself. IOW's using the term
FSB specifically refers to the connection between the CPU and chipset,
while using the term HT link could be any of many different type of
connections an HT link is used for since it's used in many more
applications than just a FSB. Some refer to the bus as a system bus, but
that's generic in nature and could even refer to the memory bus since it's
a part of the system. So, imo, the bus conncetion between the cpu and
chipset is still a FSB, thus specifically stating what the two ends
actually connect to. Simply calling it an HT link doesn't descibe any
particular bus, and shouldn't be assumed that it means a conncetion
between a xpu and its chipset, as HT links are currently being used for
other purposes. Be it convenient or not, it's still there.

They did
however move the memory controller onto the cpu, so that ram data now has
it's own data path to the CPU. This move, and not the move to an HT link
for the FSB is where the major performance gain was made. With the move to
the seperate memory bus, the FSB (now a serial HT link, instead of a
paralell bus) speed is of little importance.

As recently discussed here, HyperTransport is not a serial bus - it *is*
packetized and it is point-to-point/uni-directional but each byte-width
path has a separate clock signal and the chip/system designers have to pay
close attention to clock skew.

I'll go with you on this. Probably a paralell packet network would
describe it better.

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On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

On Tue, 06 Sep 2005 06:09:35 -0400, George Macdonald wrote:

For clearity, AMD didn't get rid of the FSB, they just stopped calling it
a FSB, even though that's what it still is, by definition.

The term FSB came about with Intel's Pentium Pro, where the dual chip
CPU/L2 cache package contained a BSB (Back Side Bus) connection between the
CPU chip and L2 cache chip. Until then the CPU system bus had carried CPU
- L2 cache data as well as I/O and memory transfers. By definition, a
FSB carried all CPU-memory and CPU-I/O transfers... but not CPU-L2
cache transfers. To me calling AMD's HT a FSB is about as valid as
continuing to use North Bridge & South Bridge for the two chips normally
used in a chipset - it's not really applicable any more but people will say
it as a convenience term

FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side cache bus"
of the P6. The P5 had no "FSB".

HT link by definition
is just that, any bus using HT technolog and is not limited to
connections between a cpu and a chipset.

Only in your mind. It is in no way an "FSB", since the term is now
meaningless. The memory bus is elsewhere, so if there *IS* an "FSB" it's
the memory bus(ses), not the HT channel. The caches are on the
"back-side" of the memory interface, not other procesors or I/O.

So given the choice of calling
the bus a FSB, or the HT link, FSB fits the bill while HT link only
describes the type of bus, not the bus itself.

FSB doesn't describe it's function at all. What's the "back side" of the
HT link?

IOW's using the term FSB
specifically refers to the connection between the CPU and chipset,

No, it doesn't. I specifically refers to the fact that the caches are on
the other side (back side) of the P6 memory bus. That architecture was
around for a while, so it stuck. There was no "FSB" in the P5
architecture. It's an invention of the P6 and should stay there, since it
no longer describes any function.


while
using the term HT link could be any of many different type of
connections an HT link is used for since it's used in many more
applications than just a FSB. Some refer to the bus as a system bus,

"System bus" works for me. I/O bus makes more sense.

but
that's generic in nature and could even refer to the memory bus since
it's a part of the system.

Since it is the intervace from the processor to the "system", it still
makes sense. "FSB" makes *no* sense, since it's not on the "front" side
of anything.

So, imo, the bus conncetion between the cpu
and chipset is still a FSB, thus specifically stating what the two ends
actually connect to. Simply calling it an HT link doesn't descibe any
particular bus, and shouldn't be assumed that it means a conncetion
between a xpu and its chipset, as HT links are currently being used for
other purposes. Be it convenient or not, it's still there.

Your opinion and $2 may be useful in a Starbuck's. They don't much care
if you're wrong, as long as you have $2.

They did
however move the memory controller onto the cpu, so that ram data now
has it's own data path to the CPU. This move, and not the move to an HT
link for the FSB is where the major performance gain was made. With the
move to the seperate memory bus, the FSB (now a serial HT link, instead
of a paralell bus) speed is of little importance.

As recently discussed here, HyperTransport is not a serial bus - it
*is* packetized and it is point-to-point/uni-directional but each
byte-width path has a separate clock signal and the chip/system
designers have to pay close attention to clock skew.

I'll go with you on this. Probably a paralell packet network would
describe it better.

Whatever, but it is *NOT* an "FSB". AMD has broken out of that system
architecture. ...much like Intel broke into it by moving the L2 traffic
to the *BACK-SIDE* bus.

--
Keith

keith wrote:
Nope. As George stated, it was in opposition the "back-side cache bus"
of the P6. The P5 had no "FSB".

Maybe in those days it was better known as the "local bus".

Yousuf Khan

On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side cache bus"
of the P6. The P5 had no "FSB".

Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
see just how many people you can convince of that.:-)

While the term may have originated the way you say, it was then later used
to indicate the connection between the CPU and the chipset. Now, that same
connection is the HT link of the K8. So it only makes sense to use the
same terminology for the very specific connection even though memory data
now has own single use bus for the memory. The FSB still carries all other
IO operations to/from the system. Once they move all this into the CPU,
there will no longer be a FSB. Until then, a duck by any other name is
still a duck.

HT link by definition is just that, any bus using HT technolog and
is not limited to connections between a cpu and a chipset.

Only in your mind. It is in no way an "FSB", since the term is now
meaningless. The memory bus is elsewhere, so if there *IS* an "FSB"
it's the memory bus(ses), not the HT channel. The caches are on the
"back-side" of the memory interface, not other procesors or I/O.

And I thought only the government could take something so simple and
fiubar.

So given the choice of calling
the bus a FSB, or the HT link, FSB fits the bill while HT link only
describes the type of bus, not the bus itself.

FSB doesn't describe it's function at all. What's the "back side" of
the HT link?

What HT link? Ht links are used everywhere. AFAIK, they don't need a
backside. They function fully indepentant of other buses. If I assume you
are talking about the HT link used to connect the K8 cpu's to the chipset,
I'd just answer that it's in the same place as back side of the K7 CPU's
FSB. You're really digging a hole for yourself here.

IOW's using the term FSB
specifically refers to the connection between the CPU and chipset,

No, it doesn't. I specifically refers to the fact that the caches are on
the other side (back side) of the P6 memory bus. That architecture was
around for a while, so it stuck. There was no "FSB" in the P5
architecture. It's an invention of the P6 and should stay there, since
it no longer describes any function.

Why are you stuck on the Pentium Pro. FSB has been used for years to
indicate the connection between the CPU and the chipset.

while
using the term HT link could be any of many different type of
connections an HT link is used for since it's used in many more
applications than just a FSB. Some refer to the bus as a system bus,

"System bus" works for me. I/O bus makes more sense.

Let's see, system buses. PCI, PCI-E, ISA, AGP, and others are all system
buses. So how are you going to distinquish which one you are talking about
if you just use system bus? Damn, I wonder if FSB would do that?:-)
I/O bus. Ditto, and you can throw HTlink into the mix too since it is also
an I/O bus.

--
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Need good help? Provide all system info with question.
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On Wed, 07 Sep 2005 05:59:41 GMT, Wes Newell
wrote:

On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side cache bus"
of the P6. The P5 had no "FSB".

Under your definition of FSB, then no AMD CPU's have ever had a FSB. Let's
see just how many people you can convince of that.:-)

No, the K7s had (the equivalent of) a FSB though I'm not sure AMD ever
called it that IIRC.

While the term may have originated the way you say, it was then later used
to indicate the connection between the CPU and the chipset. Now, that same
connection is the HT link of the K8. So it only makes sense to use the
same terminology for the very specific connection even though memory data
now has own single use bus for the memory. The FSB still carries all other
IO operations to/from the system. Once they move all this into the CPU,
there will no longer be a FSB. Until then, a duck by any other name is
still a duck.

NO - the HT is more akin to the Intel Hub interface or the VIA-Link
interconnect between memory controller/AGP chip and the I/O chip; it was
AMD's attempt to establish a standard for that type of traffic... since
Intel had locked theirs up with licensing fees. Much of the old PC North
Bridge arbitration logic is now in the K8 CPU - it has to be to route to
the various memory address spaces and for DMA transfers.

So given the choice of calling
the bus a FSB, or the HT link, FSB fits the bill while HT link only
describes the type of bus, not the bus itself.

FSB doesn't describe it's function at all. What's the "back side" of
the HT link?

What HT link? Ht links are used everywhere. AFAIK, they don't need a
backside. They function fully indepentant of other buses. If I assume you
are talking about the HT link used to connect the K8 cpu's to the chipset,
I'd just answer that it's in the same place as back side of the K7 CPU's
FSB. You're really digging a hole for yourself here.

The equivalent of FSB on a K8 CPU is inside the CPU die - anything that
gets out to HT is already defined as I/O traffic. In no way is it a FSB.

--
Rgds, George Macdonald

"Wes Newell" wrote in message
newsan.2005.09.07.06.03.43.197405@TAKEOUTverizon .net...
On Tue, 06 Sep 2005 22:18:40 -0400, keith wrote:

On Tue, 06 Sep 2005 19:13:54 +0000, Wes Newell wrote:

FSB by definition connects the CPU to the chipset.

Nope. As George stated, it was in opposition the "back-side
cache bus"
of the P6. The P5 had no "FSB".

Under your definition of FSB, then no AMD CPU's have ever had a FSB.
Let's
see just how many people you can convince of that.:-)

Wes, are you saying no AMD chip ever had an L2 cache hung off the back
of the CPU? Wow, is _my_ memory ever going south! ;-)