A computer components & hardware forum. HardwareBanter

If this is your first visit, be sure to check out the FAQ by clicking the link above. You may have to register before you can post: click the register link above to proceed. To start viewing messages, select the forum that you want to visit from the selection below.

Go Back   Home » HardwareBanter forum » Processors » AMD x86-64 Processors
Site Map Home Register Authors List Search Today's Posts Mark Forums Read Web Partners

processor arcitecture



 
 
Thread Tools Display Modes
  #1  
Old January 3rd 05, 09:13 AM
piotr
external usenet poster
 
Posts: n/a
Default processor arcitecture

I'm not an Engl. native-speaker, that's why I'm asking:
I'd like to know what means 'pipeline' (e.g. 16-bit
pipeline) in processor knowledge. Is it a bus or it is
a register meant about.


  #2  
Old January 3rd 05, 01:39 PM
Aris Adamantiadis
external usenet poster
 
Posts: n/a
Default

piotr wrote:

I'm not an Engl. native-speaker, that's why I'm asking:
I'd like to know what means 'pipeline' (e.g. 16-bit
pipeline) in processor knowledge. Is it a bus or it is
a register meant about.


Hi,

A pipeline is not a "bit" mesure, it's a depth.
You know the path of an instruction into the CPU before being executed is
very long : the cpu has to fetch it from memory to cache, from cache to
execution buffer, to decode it (understand what's it's going to do), guess
the next instruction pointer, lock the used registers, then execute it and
put back the results in the registers/memory if they are still coherent.

All of these can take like 20 clock cycles. It's a lot too much. That's why
instead of doing all of this in one clock cycle (it's not possible) the cpu
makes a pipeline containing instructions, and at each cycle, each
instruction leaves one pipeline state to another. with that trick, the cpu
virtually executes 1 instruction per clock cycle.
There are still problems like registers interlocking (2 instructions in the
pipeline need the same registers for writing) or path changes (the
instruction in the pipeline says to change the instruction pointer, so we
guess it but it was no chance the program jumped somewhere else and all
pipeline results had to be discarded.

For instance, athlon64 has 3 independant pipelines meaning you can do 3
things at once if you don't use the same registers, with one cycle.

Regards,
Aris

 




Thread Tools
Display Modes

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

vB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Forum Jump


All times are GMT +1. The time now is 12:43 PM.


Powered by vBulletin® Version 3.6.4
Copyright ©2000 - 2024, Jelsoft Enterprises Ltd.
Copyright ©2004-2024 HardwareBanter.
The comments are property of their posters.