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electronic memories capacity



 
 
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  #1  
Old November 2nd 04, 07:59 AM
>> BILLING
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Default electronic memories capacity

Why electronic memory (eg. flash) capacity is 1, 4, 8, 16, 32, 64, 128
etc. I have read that it is function of some memory parameters, but i do
not know which. Can anybody help me?
  #2  
Old November 2nd 04, 01:32 PM
James H. Fox
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" BILLING " + wrote in message
...
Why electronic memory (eg. flash) capacity is 1, 4, 8, 16, 32, 64, 128
etc. I have read that it is function of some memory parameters, but i do
not know which. Can anybody help me?


It is just the technology they use to make it. Usually, they increase the
number of transistors they can put on a chip by a factor of 4 every two
years or so, and then they increase the memory capacity accordingly. It is
not economical to increase it by a smaller factor most of the time.


  #3  
Old November 2nd 04, 01:56 PM
Mike Walsh
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Adding 1 address line will increase addressable capacity by a factor of 4, i.e. twice as many columns and twice as many rows.

"James H. Fox" wrote:

" BILLING " + wrote in message
...
Why electronic memory (eg. flash) capacity is 1, 4, 8, 16, 32, 64, 128
etc. I have read that it is function of some memory parameters, but i do
not know which. Can anybody help me?


It is just the technology they use to make it. Usually, they increase the
number of transistors they can put on a chip by a factor of 4 every two
years or so, and then they increase the memory capacity accordingly. It is
not economical to increase it by a smaller factor most of the time.


--

When replying by Email include NewSGrouP (case sensitive) in Subject

Mike Walsh
West Palm Beach, Florida, U.S.A.
  #4  
Old November 2nd 04, 02:46 PM
Graeme
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But only on devices with muxed address (DRAMs), not on flash devices (or do
some of these have multiplexed address inputs?).

"Mike Walsh" wrote in message
...

Adding 1 address line will increase addressable capacity by a factor of 4,

i.e. twice as many columns and twice as many rows.

"James H. Fox" wrote:

" BILLING " + wrote in message
...
Why electronic memory (eg. flash) capacity is 1, 4, 8, 16, 32, 64, 128
etc. I have read that it is function of some memory parameters, but i

do
not know which. Can anybody help me?


It is just the technology they use to make it. Usually, they increase

the
number of transistors they can put on a chip by a factor of 4 every two
years or so, and then they increase the memory capacity accordingly. It

is
not economical to increase it by a smaller factor most of the time.



  #5  
Old November 3rd 04, 07:51 AM
JS
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"Graeme" wrote in
:

But only on devices with muxed address (DRAMs), not on flash devices
(or do some of these have multiplexed address inputs?).



You are correct. Flash, static-ram, eeprom, rom and others typically do not
use muxed address pins. I've never seen them myself but I won't say
absolutely that they they 'never' use muxed address pins. some niche
part may do this but it is NOT common. Each additional address line/pin
doubles the number of accessible addresses and so doubles the potential
memory capacity. Its a binary thing. All forms of dynamic-ram (DRAM, SDRAM,
DDRAM, etc.) are another story but again, each additional address bit will
double the addressible memory and thus the potential memory capacity.
  #6  
Old November 3rd 04, 01:17 PM
CBFalconer
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JS wrote:
"Graeme" wrote in

But only on devices with muxed address (DRAMs), not on flash
devices (or do some of these have multiplexed address inputs?).


You are correct. Flash, static-ram, eeprom, rom and others
typically do not use muxed address pins. I've never seen them
myself but I won't say absolutely that they they 'never' use
muxed address pins. some niche part may do this but it is NOT
common. Each additional address line/pin doubles the number of
accessible addresses and so doubles the potential memory
capacity. Its a binary thing. All forms of dynamic-ram (DRAM,
SDRAM, DDRAM, etc.) are another story but again, each additional
address bit will double the addressible memory and thus the
potential memory capacity.


There is a good reason for that. Dynamic rams need two cycles, one
to address a row of bits, and the other to address a column. So
they can only use 1/2 of the address at a time. The other devices
want to address a particular address instantly, with no timing
complexities.

--
Chuck F ) )
Available for consulting/temporary embedded and systems.
http://cbfalconer.home.att.net USE worldnet address!

 




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