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Intel strikes back with a parallel x86 design
Signs and portents as JMS would say.
Stevel Jobs does a 180' and enthusiastically becomes Intel's bedfellow on the basis of a compelling roadmap. That roadmap has to be pretty darned interesting. Intel claims they aren't developing Hyperthreading anymore. But Intel now knows all the issues involved in hw threading. Why not exploit that know-how as an advantage over AMD? AMD has only a fraction of the resources that Intel has, so AMD will have a hard time catching up My speculation is that Intel will build on their HyperThread experience to design a "parallel x86". x86 CPUs have become superscalar machines. The next evolutionary step is a parallel machine. Dual-cores are only an inefficient stop-gap design that wastes transistors with duplicated or unnecessary resources (eg coherency logic between the core's caches). My ideas for a parallel x86: - thread quantums The idea is to move coarse-granularity timer-driven time-slicing into the hw so that time-slices can be instruction-granular. - thread prioritization The OS assigns static priorities to threads. The hw computes dynamic priorites according to static priority and instruction issue for a thread per quantum. - sub-threads Support for parallel programming. A reduced 80386 Task-State Segment (TSS) will be defined (avoid saving unnecessary registers such as ES/FS/GS) A variant of JUMP [TSS] with a new Thread bit defined in the TSS will spawn a sub-thread (analoguous to a UNIX child process). The sub-thread can stop by IRET [TSS]. A new WAIT [TSS] will synchronize the parent with its sub-thread. - thread exceptions A thread can raise exceptions to end or suspend itself. - cache lines have thread bits in addition to LRU bits When one cache line has to be evicted, victimize the line owned by a lower-priorty thread. - ALUs: 8 simple, 4 complex. - FPUs: 4 FADD, 4 FMUL, 2 FLDST. - deprecation of FP SIMD instruction set SIMD was a good idea for a single-thread CPU as it let the control unit issue a single-instruction for multiple-data without resource hazards. But a multi-threaded control unit would function optimally with a wide window of decomposed (SISD) instructions. |
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On Fri, 23 Sep 2005 18:11:09 GMT, Jim Brooks
wrote: Signs and portents as JMS would say. Stevel Jobs does a 180' and enthusiastically becomes Intel's bedfellow on the basis of a compelling roadmap. That roadmap has to be pretty darned interesting. Intel claims they aren't developing Hyperthreading anymore. But Intel now knows all the issues involved in hw threading. Why not exploit that know-how as an advantage over AMD? AMD has only a fraction of the resources that Intel has, so AMD will have a hard time catching up My speculation is that Intel will build on their HyperThread experience to design a "parallel x86". x86 CPUs have become superscalar machines. The next evolutionary step is a parallel machine. Dual-cores are only an inefficient stop-gap design that wastes transistors with duplicated or unnecessary resources (eg coherency logic between the core's caches). My ideas for a parallel x86: And just how much do you need to change existing software to work with your new model? Hardware is cheap, software is expensive. Make your hardware to work well with the software that exists and you'll do a LOT better than the next guy who is making hardware for software they hope to be invented in a few years time. ------------- Tony Hill hilla underscore 20 at yahoo dot ca |
#3
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In article ,
Tony Hill wrote: And just how much do you need to change existing software to work with your new model? Hardware is cheap, software is expensive. Make your hardware to work well with the software that exists and you'll do a LOT better than the next guy who is making hardware for software they hope to be invented in a few years time. If you can do that, you can almost certainly square circles, travel faster than light and produce an immortality treatment. Hardware is engineered, software is hacked up. Even those of us with pretty powerful imaginations have been unable to think of any hardware designs that would work well with the software that exists and yet not violate the laws of physics. Regards, Nick Maclaren. |
#4
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Jim Brooks wrote:
Signs and portents as JMS would say. Stevel Jobs does a 180' and enthusiastically becomes Intel's bedfellow on the basis of a compelling roadmap. That roadmap has to be pretty darned interesting. Intel claims they aren't developing Hyperthreading anymore. But Intel now knows all the issues involved in hw threading. Why not exploit that know-how as an advantage over AMD? AMD has only a fraction of the resources that Intel has, so AMD will have a hard time catching up I would hardly call the knowledge they gained in hyperthreading to be knowledge that will come in handy later. Whatever they learned about HT was only relevent to a Pentium 4, it can't apply to Pentium M. My speculation is that Intel will build on their HyperThread experience to design a "parallel x86". x86 CPUs have become superscalar machines. The next evolutionary step is a parallel machine. Dual-cores are only an inefficient stop-gap design that wastes transistors with duplicated or unnecessary resources (eg coherency logic between the core's caches). My ideas for a parallel x86: - thread quantums snip You're from the comp.arch group aren't you? Yousuf Khan |
#5
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"Yousuf Khan" wrote in message ... Jim Brooks wrote: Signs and portents as JMS would say. Stevel Jobs does a 180' and enthusiastically becomes Intel's bedfellow on the basis of a compelling roadmap. That roadmap has to be pretty darned interesting. Intel claims they aren't developing Hyperthreading anymore. But Intel now knows all the issues involved in hw threading. Why not exploit that know-how as an advantage over AMD? AMD has only a fraction of the resources that Intel has, so AMD will have a hard time catching up I would hardly call the knowledge they gained in hyperthreading to be knowledge that will come in handy later. Whatever they learned about HT was only relevent to a Pentium 4, it can't apply to Pentium M. My speculation is that Intel will build on their HyperThread experience to design a "parallel x86". x86 CPUs have become superscalar machines. The next evolutionary step is a parallel machine. Dual-cores are only an inefficient stop-gap design that wastes transistors with duplicated or unnecessary resources (eg coherency logic between the core's caches). My ideas for a parallel x86: - thread quantums snip You're from the comp.arch group aren't you? Yousuf Khan doesn't ring any bells from comp.arch Has only a few posts on groups.google.com search, my guess is comp.sys.intel |
#6
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Jim Brooks wrote:
Signs and portents as JMS would say. Stevel Jobs does a 180' and enthusiastically becomes Intel's bedfellow on the basis of a compelling roadmap. That roadmap has to be pretty darned interesting. Intel claims they aren't developing Hyperthreading anymore. But Intel now knows all the issues involved in hw threading. Why not exploit that know-how as an advantage over AMD? AMD has only a fraction of the resources that Intel has, so AMD will have a hard time catching up I would hardly call the knowledge they gained in hyperthreading to be knowledge that will come in handy later. Whatever they learned about HT was only relevent to a Pentium 4, it can't apply to Pentium M. That's like saying none of the knowledge gained from the P6 design carried over to the Williamette design. About the Mac, Jobs looked at the roadmaps of both Intel and AMD. There were other factors, but Jobs was more intrigued by Intel's. Why? Turning to the server-blade market, when you need more racks of blades, the consideration is packing as much processing performance per watt (and space). There is only so much instruction parallelism in one thread of code. Single-threaded superscalars core often stall because of data dependencies, resource locks, cache misses,etc. Multi-threaded (parallel) cores are the future. |
#7
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Jim Brooks writes:
My speculation is that Intel will build on their HyperThread experience to design a "parallel x86". x86 CPUs have become superscalar machines. The next evolutionary step is a parallel machine. Dual-cores are only an inefficient stop-gap design that wastes transistors with duplicated or unnecessary resources (eg coherency logic between the core's caches). intel back to the future? old posting http://www.garlic.com/~lynn/2001n.html#83 CM-5 Thinking Machines, Supercomputers that includes pieces of some old news articles ... inclucing an NYT article from 6/15/92 titled Foray into Mainstream for Parallel Computing. some number of the efforts from the period were parallel x86s ... also can anybody say Intel Paragon? how 'bout ncube: http://en.wikipedia.org/wiki/NCUBE iPSC http://www.cs.kuleuven.ac.be/museum/...yosotis-E.html IPSC/2 hypercube http://portal.acm.org/citation.cfm?id=255159 red asci, originally pentium pro, then updated to pentium II .. http://en.wikipedia.org/wiki/Intel_ASCI_Red http://www.sandia.gov/ASCI/Red/ in the mid-90s, there there were so many people tied up in working on such stuff that one such new mpp project ... looking around for people to lead the effort, got around to asking my wife and me. I ran thru all the names I could think of them to ask ... and they pointed out that everybody I named, were all busy, tied up on something else -- Anne & Lynn Wheeler | http://www.garlic.com/~lynn/ |
#8
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Del Cecchi wrote:
"Yousuf Khan" wrote in message ... Jim Brooks wrote: My ideas for a parallel x86: - thread quantums snip You're from the comp.arch group aren't you? doesn't ring any bells from comp.arch Has only a few posts on groups.google.com search, my guess is comp.sys.intel Oh well, it just seems the comp.arch group produces an abundance of dreamers. It's like a Beatnik Speakeasy for chip geeks. It's like the technological equivalent of artsies. All of the "Alpha coulda ruled the world types" seem to hang out there. Yousuf Khan |
#9
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"YKhan" wrote in message ups.com... Del Cecchi wrote: "Yousuf Khan" wrote in message ... Jim Brooks wrote: My ideas for a parallel x86: - thread quantums snip You're from the comp.arch group aren't you? doesn't ring any bells from comp.arch Has only a few posts on groups.google.com search, my guess is comp.sys.intel Oh well, it just seems the comp.arch group produces an abundance of dreamers. It's like a Beatnik Speakeasy for chip geeks. It's like the technological equivalent of artsies. All of the "Alpha coulda ruled the world types" seem to hang out there. Yousuf Khan Along with a few hard headed circuit designers..... and some highly qualified and knowledgable folks who have btdt. del |
#10
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Jim Brooks wrote:
Signs and portents as JMS would say. Stevel Jobs does a 180' and enthusiastically becomes Intel's bedfellow on the basis of a compelling roadmap. That roadmap has to be pretty darned interesting. Intel claims they aren't developing Hyperthreading anymore. But Intel now knows all the issues involved in hw threading. Why not exploit that know-how as an advantage over AMD? AMD has only a fraction of the resources that Intel has, so AMD will have a hard time catching up My speculation is that Intel will build on their HyperThread experience to design a "parallel x86". x86 CPUs have become superscalar machines. The next evolutionary step is a parallel machine. Dual-cores are only an inefficient stop-gap design that wastes transistors with duplicated or unnecessary resources (eg coherency logic between the core's caches). My ideas for a parallel x86: - thread quantums The idea is to move coarse-granularity timer-driven time-slicing into the hw so that time-slices can be instruction-granular. - thread prioritization The OS assigns static priorities to threads. The hw computes dynamic priorites according to static priority and instruction issue for a thread per quantum. - sub-threads Support for parallel programming. A reduced 80386 Task-State Segment (TSS) will be defined (avoid saving unnecessary registers such as ES/FS/GS) A variant of JUMP [TSS] with a new Thread bit defined in the TSS will spawn a sub-thread (analoguous to a UNIX child process). The sub-thread can stop by IRET [TSS]. A new WAIT [TSS] will synchronize the parent with its sub-thread. - thread exceptions A thread can raise exceptions to end or suspend itself. - cache lines have thread bits in addition to LRU bits When one cache line has to be evicted, victimize the line owned by a lower-priorty thread. - ALUs: 8 simple, 4 complex. - FPUs: 4 FADD, 4 FMUL, 2 FLDST. - deprecation of FP SIMD instruction set SIMD was a good idea for a single-thread CPU as it let the control unit issue a single-instruction for multiple-data without resource hazards. But a multi-threaded control unit would function optimally with a wide window of decomposed (SISD) instructions. We'll see this CPU introduced in the blueberry iMac in Q3 2006 ;-) |
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