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#1
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how can I use a signal defined in one Architecture to another Architecture
Hello everybody,
I want to use the signal defined in one architecture in VHDL to another architecture. I have two architecture in the same .vhd file and I am using Component mapping. I required the result of calculation of a signal to be used in second architecture. Can any one tell how to defined signal so that it is globally visible to other architectures. Regards Khan |
#2
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Muhammad Khan wrote:
I want to use the signal defined in one architecture in VHDL to another architecture. I have two architecture in the same .vhd file and I am using Component mapping. I required the result of calculation of a signal to be used in second architecture. Can any one tell how to defined signal so that it is globally visible to other architectures. Hello Muhammad, this is a common question. The clean way for handling this is to feed the signal through the port maps. Regards, Mario -- ---------------------------------------------------------------------- Digital Force / Mario Trams Chemnitz University of Technology http://www.tu-chemnitz.de/~mtr Dept. of Computer Science Tel.: (+49) 371 531 1660 Chair of Computer Architecture Fax.: (+49) 371 531 1818 ---------------------------------------------------------------------- |
#3
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Hi Khan,
If you declare a signal in a package and you include the package then the signal can be globally used by all architectures that reference that package. This is for simulation only and will not work for synthesis. Jon (Muhammad Khan) wrote in message . com... Hello everybody, I want to use the signal defined in one architecture in VHDL to another architecture. I have two architecture in the same .vhd file and I am using Component mapping. I required the result of calculation of a signal to be used in second architecture. Can any one tell how to defined signal so that it is globally visible to other architectures. Regards Khan |
#4
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Jon wrote: Hi Khan, If you declare a signal in a package and you include the package then the signal can be globally used by all architectures that reference that package. This is for simulation only and will not work for synthesis. This will work for synthesis in Synplify Pro 7.3. Jon (Muhammad Khan) wrote in message . com... Hello everybody, I want to use the signal defined in one architecture in VHDL to another architecture. I have two architecture in the same .vhd file and I am using Component mapping. I required the result of calculation of a signal to be used in second architecture. Can any one tell how to defined signal so that it is globally visible to other architectures. Regards Khan |
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