memory mapped IO: device registers mapped to virtual memory or physical memory?

Look up DVMA (Direct Virtual Memory Access). Some systems
allow devices to deal in virtual memory addresses, passing
their address requests through the MMU to resolve them.
That means that a mapping of not necessarily contigous
physical pages to a contiguous range of virtual memory
can be done, and the device doesn't need to be able to
do scatter/gather operations (list of pages to transfer
to/from all at once). The old sun4m (SPARC/Sbus) systems
typically worked like that.

Windows supports this fully with their notion of "adapter object" and "logical
address" (the device-side address).

More so: AGP bus works exactly this way, its "MMU" is called GART - Graphics
Address Remap Table or such. The organization of this table is
chipset-specific, and thus the "AGP driver" for Windows.

--
Maxim Shatskih, Windows DDK MVP
StorageCraft Corporation

http://www.storagecraft.com

Maxim S. Shatskih wrote On 02/07/06 17:09,:
Look up DVMA (Direct Virtual Memory Access). Some systems
allow devices to deal in virtual memory addresses, passing
their address requests through the MMU to resolve them.
That means that a mapping of not necessarily contigous
physical pages to a contiguous range of virtual memory
can be done, and the device doesn't need to be able to
do scatter/gather operations (list of pages to transfer
to/from all at once). The old sun4m (SPARC/Sbus) systems
typically worked like that.


Windows supports this fully with their notion of "adapter object" and "logical
address" (the device-side address).

More so: AGP bus works exactly this way, its "MMU" is called GART - Graphics
Address Remap Table or such. The organization of this table is
chipset-specific, and thus the "AGP driver" for Windows.

Well, I guess there are more things in Heaven and
Earth than are dreamt of in my philosophy. Seems like
an awfully strange way to arrange things -- but live
and learn. What will they think of next? And is there
the faintest chance it will make sense? ;-)

--

In article ,
Eric Sosman writes:


Maxim S. Shatskih wrote On 02/07/06 17:09,:
Look up DVMA (Direct Virtual Memory Access). Some systems
allow devices to deal in virtual memory addresses, passing
their address requests through the MMU to resolve them.
That means that a mapping of not necessarily contigous
physical pages to a contiguous range of virtual memory
can be done, and the device doesn't need to be able to
do scatter/gather operations (list of pages to transfer
to/from all at once). The old sun4m (SPARC/Sbus) systems
typically worked like that.


Windows supports this fully with their notion of "adapter object" and "logical
address" (the device-side address).

More so: AGP bus works exactly this way, its "MMU" is called GART - Graphics
Address Remap Table or such. The organization of this table is
chipset-specific, and thus the "AGP driver" for Windows.

Well, I guess there are more things in Heaven and
Earth than are dreamt of in my philosophy. Seems like
an awfully strange way to arrange things -- but live
and learn. What will they think of next? And is there
the faintest chance it will make sense? ;-)

Time makes all things make sense, or at least allows one to discover
perspectives under which someone might have thought they made sense.
That is, it isn't always what they'll think of next, it may be what
they already thought of some time back.

(I'm assuming that someone who works for Sun, but didn't already have
the sun4m DVMA counter-example staring them in the face, is younger than
I am...)

I wonder if cache coherency issues didn't kill some of these things.

When someone comes up with really fast memory that's still low power and
very high density, and maybe some really slick electrical/optical
components, allowing optical memory interconnects (so distance won't
matter so much), it seems like it will cut so much complication out;
wouldn't have to work so damn hard on cache coherency if you didn't need a
cache, NUMA would only be needed with geographic level redundancy, etc. :-)


But from what I gather the poster that mentioned Windows was saying, both
operating systems (Solaris and Windows) have frameworks that allow for the
possibility of devices operating either in terms of physical or virtual
addresses, at least in some cases. So potentially they both serve to
abstract the hardware in that way as in so many others.

--
http://www.smart.net/~rlhamil

Lasik/PRK theme music:
"In the Hall of the Mountain King", from "Peer Gynt"

Olumide wrote:
Hi -

I know memory mapped IO is about mapping device/controller registers to
memory space in order to reduce the number of processor instructions
(and simplify device driver writing) . My question is: are device
registers mapped to virtual memory or physical memory? I suspect the
former, and I have looked up a number of texts but everyone just seems
to skirt about the issue.

I think there is a more important issue here, you say 'simplify device
driver writing', I'd counter by saying 'produce a driver that works only
on the platform and OS version you develop it on'

The OS provides you with and API to protect you form the shifting sands
of kernel updates and endian issues.

--
Ian Collins.