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PCI settings on 7501 chipset
Does anyone know what the PCI transaction settings are for the 7500, 7501,
7505 chipsets and/or where to find them? For example, When my PCI64 device issues a master DMA burst transaction, the chipset sends retry signals down to my device while it prefetches the host memory. How many cycles does this take? How much data is prefetched? How can I change these settings? Is there one MB manufacturer that makes it easier to change these than another? Thanks, Brannon |
#2
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On 16 Jan 2004 11:27:08 EST, "Brannon King"
wrote: Does anyone know what the PCI transaction settings are for the 7500, 7501, 7505 chipsets and/or where to find them? For example, When my PCI64 device issues a master DMA burst transaction, the chipset sends retry signals down to my device while it prefetches the host memory. Perfectly normal. How many cycles does this take? Depends when the target memory bank is available. If it has to close an open page and perform a precharge, start the read, and then accumulate data for the request, that's longer than hitting an open page. How much data is prefetched? "Prefetched"? You mean *after* the first line of data? How much did your device ask for? If it asked for a single line there may not be any additional data prefetched, or there may be one additional line. If it used a read multiple, perhaps all of the prefetch buffers are committed to that thread. Time to dig into the chipset specs. How can I change these settings? Well, you can't change memory latency ;-) but you may be able to change some of the prefetching behavior by twiddling bits in the MCH. You'll need at least one yellow book, I imagine. And to get that you need an NDA. Good luck ;-) Is there one MB manufacturer that makes it easier to change these than another? Only if they plumbed the pertinent bits into the bios and gave access to them via the cmos setup utility. Not very likely. /daytripper |
#3
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Thanks for the reply. I usually request either a 2kB or a 4kB chunk, and I'm
seeing about 70MB/s with that (no scatter-gather/split). My data going the other direction is about 230MB/s, but I understand this slower master read is typical behaviour for PCI (and PCI64, which I'm using.) I was just trying to increase that rate some. "daytripper" wrote in message ... On 16 Jan 2004 11:27:08 EST, "Brannon King" wrote: Does anyone know what the PCI transaction settings are for the 7500, 7501, 7505 chipsets and/or where to find them? For example, When my PCI64 device issues a master DMA burst transaction, the chipset sends retry signals down to my device while it prefetches the host memory. Perfectly normal. How many cycles does this take? Depends when the target memory bank is available. If it has to close an open page and perform a precharge, start the read, and then accumulate data for the request, that's longer than hitting an open page. How much data is prefetched? "Prefetched"? You mean *after* the first line of data? How much did your device ask for? If it asked for a single line there may not be any additional data prefetched, or there may be one additional line. If it used a read multiple, perhaps all of the prefetch buffers are committed to that thread. Time to dig into the chipset specs. How can I change these settings? Well, you can't change memory latency ;-) but you may be able to change some of the prefetching behavior by twiddling bits in the MCH. You'll need at least one yellow book, I imagine. And to get that you need an NDA. Good luck ;-) Is there one MB manufacturer that makes it easier to change these than another? Only if they plumbed the pertinent bits into the bios and gave access to them via the cmos setup utility. Not very likely. /daytripper |
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