On Thu, 15 Sep 2005 00:10:27 GMT, Wes Newell
wrote:

On Wed, 14 Sep 2005 18:47:12 +0000, Scott Lurndal wrote:

It is clearly not a bus. The northbridge is integrated into the
processor die. The other end of an HT link is either another
processor socket or a southbridge.

Hope that answers your query.

It's an answer, just wrong. First, it is a bus, and second, it doesn't
connect to the chipset southbridge, it connects to the chipset
northbridge. Although AMD refers to the logic that splits the memory data
to the internal memory controller a northbridge, well I guess they can
call it whatever they like. The HT link (FSB, CPU bus or whatever you
want to call it) that connects to the chipset connects to the chipset
northbridge (the SIS755 In my case). The SIS755 connects to the
southbridge over a preprietary MUtiol bus. I guess at this point we have
to except that there's 2 northbridges. One in the CPU, and one in the
chipset. Either that or call either AMD or ALL the chipset manufactures
liars for calling there chip a northbridge too. Clearly, what used to be
all done in the chipset northbridge is now partly done in both the cpu and
chipset.

Well, where there are still two chips for the "chipset" -- not the case for
nForce3/4 -- there is a *small* amount of north bridge functionality in the
chip at the other end of the CPU-HT I/O-link: a mezzanine bus to AGP &
PCI-X or the PCI-e x16 graphics link... and maybe some other high
priority/speed link like multi-Gig network but that's piddly compared with
a memory controller and all the arbitration logic plus snooping to the FSB
in a real north bridge. In fact Intel dropped the term North Bridge years
ago and uses MCH for umm, Memory Controller Hub... and AMD would call your
"SIS755 north bridge" a HyperTransport Tunnel. Says it all from my POV -
it doesn't even talk like a duck.:-)

--
Rgds, George Macdonald