Jon wrote:

Hi Khan,
If you declare a signal in a package and you include the package
then the signal can be globally used by all architectures that
reference that package. This is for simulation only and will not
work for synthesis.


This will work for synthesis in Synplify Pro 7.3.



Jon


(Muhammad Khan) wrote in message . com...

Hello everybody,

I want to use the signal defined in one architecture in VHDL to
another architecture. I have two architecture in the same .vhd file
and I am using Component mapping. I required the result of calculation
of a signal to be used in second architecture. Can any one tell how to
defined signal so that it is globally visible to other architectures.

Regards

Khan