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Old March 8th 10, 07:47 AM posted to alt.comp.hardware.amd.x86-64,alt.comp.hardwre.amd.x86-64,alt.comp.periphs.mainboard.msi-microstar
Ant[_3_]
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Default "TLB parity error in virtual array; TLB error 'instruction"?

On 3/7/2010 10:22 PM PT, Paul typed:

http://en.wikipedia.org/wiki/Transla...okaside_buffer

TLB stands for Translation Lookaside Buffer.
It translates from virtual addresses to physical addresses.
And apparently, according to the AMD documentation, it is protected by
parity.
It is part of the processor.

A question would be, if it was a real error, why weren't there crash
symptoms or side effects ? If an incorrect mapping from virtual space


Wouldn't kernel panics be one of them?


to physical occurred, you'd think there would be consequences. (Maybe
the entry is automatically invalidated and reloaded via page table walk ?)


[shrugs]


The AMD processor apparently has BIST or built-in self test, for memory
structures inside the processor. This document is not at all clear, on
whether you'd have that implemented on a typical desktop motherboard.
It is an optional operation, that would occur early after powerup.
It would allow bad internal memory inside the processor to be detected,
before a computer boots. There is a bit in a special register, that
contains the test result, if the test was triggered.

(Section 14.1.1 PDF page 395 "Programmers Manual Vol.2")
http://support.amd.com/us/Processor_TechDocs/24593.pdf


Now, this is over my head. Is there a way to test this with softwares?
Does memtest86+ v4.00 test for this? I already tried compiling, unraring
10+ GB of datas, running sys_basher, and memtest86+ v4.0 (passed a few
weeks ago + this morning = five tests total). It doesn't seem to
stress/overload and temperatures related since most kernel panics
happened when mostly idled!
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