wrote:
I read a review at wccftech, which has this intriguing sentence:

With memory access modes, users can select between UMA (maximum memory bandwidth) and NUMA (lowest latency) modes.

So what is going on? I guess there are 2 memory controllers which are
married to a CPU die, but can be linked to act like a shared memory beast.

See "Memory Modes", about 70% down the page.

https://en.wikichip.org/wiki/amd/microarchitectures/zen

*******

That page is for Zen. The page for Zen2 is barely started.

https://en.wikichip.org/wiki/amd/mic...tectures/zen_2

Paul